ARM HDLCD Driver Merged Into DRM-Next
Landing today in DRM-Next for eventual merging into the Linux 4.5 kernel source tree is the ARM HDLCD driver.
HLCD in this context is short for ARM's High Definition Color LCD controller. The driver source is in Git is just over one thousand lines of code. This driver was officially developed at ARM.
The HDLCD is described at the ARM Information Center as "An ARM HDLCD controller in the Cortex-A5 MPCore test chip provides graphic display capabilities. The controller is a frame buffer device that is capable of displaying up to 1920×1080p pixel resolution at 60Hz with a 165MHz pixel clock from OSCCLK3. The MultiMedia Bus (MMB) connects the 24-bit RGB data directly between the test chip and the motherboard through header HDRY. The multiplexer FPGA on the motherboard can select this bus to drive the analog and digital interfaces for the DVI connector. The HDLCD frame buffer is located in DDR2 memory serviced by the DMC from the test chip bus matrix. This ensures maximum data bandwidth between the Cortex-A5 MPCore cluster, the HDLCD controller, and DDR2 memory without accessing off-chip devices."
There is more information on this controller over here as well. This controller is found on devices like the Juno and ARM TC2 Coretile.
HLCD in this context is short for ARM's High Definition Color LCD controller. The driver source is in Git is just over one thousand lines of code. This driver was officially developed at ARM.
The HDLCD is described at the ARM Information Center as "An ARM HDLCD controller in the Cortex-A5 MPCore test chip provides graphic display capabilities. The controller is a frame buffer device that is capable of displaying up to 1920×1080p pixel resolution at 60Hz with a 165MHz pixel clock from OSCCLK3. The MultiMedia Bus (MMB) connects the 24-bit RGB data directly between the test chip and the motherboard through header HDRY. The multiplexer FPGA on the motherboard can select this bus to drive the analog and digital interfaces for the DVI connector. The HDLCD frame buffer is located in DDR2 memory serviced by the DMC from the test chip bus matrix. This ensures maximum data bandwidth between the Cortex-A5 MPCore cluster, the HDLCD controller, and DDR2 memory without accessing off-chip devices."
There is more information on this controller over here as well. This controller is found on devices like the Juno and ARM TC2 Coretile.
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