RISC-V With Linux 6.7 Gains Optimized TLB Flushing, Software Shadow Call Stacks
On the RISC-V hardware side as already mentioned is initial support for Sophgo RISC-V chips including that forthcoming 64 core RISC-V CPU. On the RISC-V architecture side are also some continued innovations for Linux 6.7.
The Milk-V Pioneer is a very interesting 64-bot mATX workstation board that should begin shipping next month at $1499 USD. I've since confirmed there will be review hardware coming to Phoronix for checking out this interesting creation.
Merged last week was support for cbo.zero in user-space, support for CBOs on ACPI-based RISC-V systems, support for software shadow call stacks, improvements for the T-Head cache flushing operations, and other clean-ups and fixes.
This software-based Shadow Call Stack support for RISC-V relies on compiler instrumentation for storing and checking the return memory address for enhancing the security. The RISC-V Shadow Call Stack support as with SCS for other CPU architectures is intended to help fend off accidental or malicious overwrites. The RISC-V SCS support depends on LLVM Clang 17 and later for compiling the kernel with no GCC support currently for this functionality on RISC-V.
Meanwhile sent out today was a secondary pull request of more RISC-V changes for Linux 6.7. This latest pull has support for handling misaligned accesses in S-mode, performance improvements for TLB flushing, support for many new relocations in the module loader, and other enhancements.