RISC-V News Archives


94 RISC-V open-source and Linux related news articles on Phoronix since 2016.

LibreOffice Enables RISC-V 64-bit Support
LibreOffice Enables RISC-V 64-bit Support

If the royalty free open-source processor ISA RISC-V is to enjoy success on the Linux desktop, obviously it needs an office suite... LibreOffice as the open-source office suite alternative to Microsoft Office is now seeing proper RISC-V 64-bit support.

11 November 2022 - LibreOffice + RISC-V - 18 Comments
RISC-V Lands New Extensions In Linux 6.0
RISC-V Lands New Extensions In Linux 6.0

Last week was the main set of RISC-V updates for Linux 6.0 that included improving Svpbmt support, a more robust default kernel configuration, and other improvements. A secondary set of RISC-V CPU architecture updates has now been merged for Linux 6.0.

13 August 2022 - Linux 6.0 RISC-V - 3 Comments
The First RISC-V Laptop Announced With Quad-Core CPU, 16GB RAM, Linux Support
The First RISC-V Laptop Announced With Quad-Core CPU, 16GB RAM, Linux Support

RISC-V International has relayed word to us that in China the DeepComputing and Xcalibyte organizations have announced pre-orders on the first RISC-V laptop intended for developers. The "ROMA" development platform features a quad-core RISC-V processor, up to 16GB of RAM, up to 256GB of storage, and should work with most RISC-V Linux distributions.

1 July 2022 - DeepComputing + Xcalibyte - 83 Comments
Linux 5.19 Adding Support For The PolarBerry RISC-V FPGA Board
Linux 5.19 Adding Support For The PolarBerry RISC-V FPGA Board

A few days ago the RISC-V pull request landed in Linux 5.19 with support for RISC-V 32-bit (RV32) binaries on RV64, enabling the new Svpbmt extension, and other improvements. On Friday a secondary set of RISC-V changes were sent in for Linux 5.19 that includes adding the DeviceTree files for another new RISC-V board.

3 June 2022 - RISC-V PolarBerry - 8 Comments
MIPS Claims "Best-In-Class Performance" With New RISC-V eVocore CPUs
MIPS Claims "Best-In-Class Performance" With New RISC-V eVocore CPUs

MIPS Tech is no longer working on their MIPS CPU instruction set architecture but has been taking on RISC-V based designs. Today the company made the bold announcement for their new eVocore P8700 and I8500 multiprocessor IP cores that they offer "Best-In-Class Performance and Scalability."

10 May 2022 - MIPS RISC-V - 36 Comments
RISC-V CPU Idle Support, Other RISC-V Improvements Merged Into Linux 5.18

Last week the main RISC-V pull for Linux 5.18 brought Sv57 five level page table support, improved PolarFire SoC support, an optimized MEMMOVE code, support for Restartable Sequences, and more. A second batch of RISC-V feature updates were sent out this week and now merged for making Linux 5.18 even better for this open processor ISA.

3 April 2022 - RISC-V CPU Idle - Add A Comment
Linux 5.18 To Bring RISC-V sv57 Support For 5-Level Page Tables
Linux 5.18 To Bring RISC-V sv57 Support For 5-Level Page Tables

It was just with Linux 5.17 that its RISC-V code adds "sv48" support for being able to handle more system memory by offering 48-bit virtual address space support. Now for Linux 5.17 there is "sv57" support prepared for 57-bit virtual address space support with five level page table handling.

25 February 2022 - RISC-V sv57 - 1 Comment
SiFive Shifting Production Focus To Next-Gen HiFive Development Board
SiFive Shifting Production Focus To Next-Gen HiFive Development Board

SiFive's HiFive Unmatched is the best, readily available RISC-V developer board at the moment with enough horsepower for modest development/porting work and continues seeing improvements with the mainline Linux kernel. But availability on HiFive Unmatched is beginning to dry up and SiFive isn't planning on any further production runs as it begins focusing on the board's successor.

21 January 2022 - HiFive Unmatched Reaching End Of Line - 58 Comments
Imagination Announces "Catapult" RISC-V CPU Family
Imagination Announces "Catapult" RISC-V CPU Family

With Imagination Technologies having sold off what was MIPS Technologies several years ago and that CPU architecture having been abandoned now, Imagination today announced "Catapult" as their new family of RISC-V processor IP.

6 December 2021 - RISC-V CPUs - 26 Comments
Open-Source FPGA-Based RISC-V GPGPU That Supports OpenCL 1.2

While there was the Libre RISC-V GPU effort aiming to provide an open-source GPU accelerator based on RISC-V, it ultimately turned into Libre-SOC with a focus now on the POWER ISA. Meanwhile Vortex is continuing to mature as an open-source, FPGA-based RISC-V GPGPU processor.

30 November 2021 - Vortex GPGPU - 16 Comments
Transparent Hugepages Are Coming To RISC-V On Linux

The Linux kernel's RISC-V support continues picking up remaining features not yet wired up beyond the base architecture support. The latest is transparent hugepages (THP) to be supported for RISC-V with Linux 5.14.

12 June 2021 - THP For RISC-V - 7 Comments
Intel Reportedly Interested In Acquiring RISC-V Firm SiFive

Back in March during the announcement of Intel Foundry Services it was mentioned that SiFive and Intel were working together to allow RISC-V chips to be fabbed within Intel's facilities. Additionally, Intel Capital previously invested in SiFive during prior funding rounds. Now it turns out Intel is reportedly positioning to potentially acquire SiFive.

10 June 2021 - Intel Buying Out SiFive? - 49 Comments
A Number Of Exciting RISC-V Improvements For Linux 5.13

From bringing up the PolarFire ICICLE SoC to adding support for KProbes, FORTIFY_SOURCE, and other new kernel features for the RISC-V architecture, the Linux 5.13 kernel changes are exciting for this open-source processor ISA.

6 May 2021 - PolarFire To KProbes - 5 Comments
SiFive FU740 PCIe Support Queued Ahead Of Linux 5.13

Arguably the most interesting RISC-V board announced to date is SiFive's HiFive Unmatched with the FU740 RISC-V SoC that features four U74-MC cores and one S7 embedded core. The HiFive Unmatched also has 16GB of RAM, USB 3.2 Gen 1, one PCI Express x16 slot (operating at x8 speeds), an NVMe slot, and Gigabit Ethernet. The upstream kernel support for the HiFive Unmatched and the FU740 SoC continues.

11 April 2021 - FU740 PCI Express - 12 Comments
Alibaba Reports Their XT910 RISC-V Core To Be Faster Than An Arm Cortex-A73

A few weeks back Alibaba announced the "XT910" as the fastest RISC-V processor featuring 16 cores and clock speeds up to 2.5GHz while being manufactured on a 12nm node. This by far beats most RISC-V hardware currently available and now at this week's Hot Chips conference the Chinese company is reporting that the XT910 is faster than an Arm Cortex-A73.

18 August 2020 - Alibaba XT910 - 82 Comments
RISC-V UEFI Linux Support Under Review

Following Linux's UEFI code getting cleaned up earlier this year in preparation for RISC-V support being added and then some early RISC-V UEFI patches, a more comprehensive set of patches for enabling UEFI support on RISC-V under Linux have been sent out.

28 June 2020 - RISC-V + UEFI - 8 Comments
Linux Kernel Continues Prepping For RISC-V's Updated Supervisor Binary Interface

RISC-V's Supervisor Binary Interface "SBI" is the interface between the platform-specific firmware and the running operating system or hypervisor for interacting with the supervisor execution environment in the higher privileged mode. The Linux kernel has been working to support a newer version of the SBI that is more extensible moving forward.

12 February 2020 - Supervisor Binary Interface v0.2 - 4 Comments
NEOX V Announced By Think Silicon As First RISC-V 3D GPU

While there has been the Libre RISC-V community-driven effort to create a RISC-V graphics processor that basically amounts to a RISC-V core with vector extensions/improvements and running a Vulkan software implementation (though they are now reportedly eyeing POWER instead of RISC-V), Think Silicon has announced the first actual RISC-V ISA based 3D graphics processor.

2 December 2019 - NEOX V - 17 Comments

94 RISC-V news articles published on Phoronix.