RISC-V News Archives

In addition to the many x86/x86_64 and AArch64 improvements this round for Linux 6.7, on the RISC-V architecture side are some exciting kernel advancements too.

Patches posted this week by SiFive for the Linux kernel provide cryptographic implementations of various functions inside the Linux kernel using the processor ISA's vector crypto extensions.

As we approach the end of 2023, sadly, the real-time kernel "PREEMPT_RT" support still hasn't been mainlined... The main blocker pending is still the ongoing work around non-blocking consoles / threaded console handling to then allow the few dozen remaining out-of-tree RT kernel patches to be merged. The good news is that when the PREEMPT_RT support is ready for mainline, it looks like the RISC-V architecture support will also be real-time friendly too.

Patches have been posted to the Linux kernel mailing list in an effort to mainline support for the Milk-V Duo RISC-V development platform with the basic board retailing for $9.

More RISC-V architecture updates were merged this weekend for the ongoing Linux 6.6 merge window.

Palmer Dabbelt sent out the initial batch of RISC-V processor architecture updates for the Linux 6.6 kernel port.

The GNU Compiler Collection 14 (GCC 14) will feature support for the new RISC-V processor ISA vector cryptographic extensions.

While the upstream Linux kernel support for RISC-V continues to improve with new ISA features, support for more RISC-V SoCs, and other enhancements, in some areas the open-source RISC-V code continues to play catch-up with the other mature architectures supported by the Linux kernel. One of the areas still pending is enabling KASLR support for RISC-V on Linux to enhance system security.

Support for RISC-V's Vector ISA is now expected to be merged for the upcoming Linux 6.5 kernel merge window.

Linux Foundation Europe has announced the RISC-V Software Ecosystem (RISE) Project to help facilitate more performant, commercial-ready software for the RISC-V processor architecture.

One of the missing RISC-V features now in place for the in-development Linux 6.4 kernel is system hibernation / suspend-to-disk support.

Being merged today into the GCC 13 compiler is the set of T-Head vendor extensions to the RISC-V ISA. This set of vendor extensions is designed to augment the RISC-V ISA and provide faster and more energy efficient capabilities.

The RISC-V architecture updates were merged this Saturday for the Linux 6.3 merge window.

A Phoronix reader pointed out that there are initial code that landed for adding RISC-V processor support to Microsoft's .NET runtime.

While there has been much work on the Linux kernel's RISC-V CPU architecture support, a feature not tackled until now has been the Kernel Address Space Layout Randomization (KASLR) support for randomizing the kernel mapping to enhance system security.

While there is a lot to love about RISC-V, with the plethora of RISC-V extensions some of the acronyms are hard to digest. The latest example is the Linux kernel patches for "zisslpcfi", which is the RISC-V extension around Control-Flow Integrity (CFI) support for RISC-V processors.

While the open RISC-V processor architecture has proven to be highly successful, one of the features that it hasn't yet supported with the Linux kernel to this point has been system hibernation / suspend-to-resume, but that support is now on the way.

The RISC-V processor architecture changes were merged this week for the Linux 6.2 cycle.

If the royalty free open-source processor ISA RISC-V is to enjoy success on the Linux desktop, obviously it needs an office suite... LibreOffice as the open-source office suite alternative to Microsoft Office is now seeing proper RISC-V 64-bit support.

For those working on RISC-V software development on bare metal hardware, the in-development LLVM Clang 16 compiler has added support for allowing "-mtune=native" and "-mcpu=native" to work properly on this CPU ISA.

Not that you are likely to connect a CD/DVD drive to a RISC-V system in 2022+, but RISC-V's default kernel configuration with the upcoming Linux 6.1 kernel is adding support for CD-ROM file-systems.

Last week was the main set of RISC-V updates for Linux 6.0 that included improving Svpbmt support, a more robust default kernel configuration, and other improvements. A secondary set of RISC-V CPU architecture updates has now been merged for Linux 6.0.

Each new kernel cycle there continues to be more maturity to the RISC-V processor architecture code. With Linux 6.0 there are a few new features wired up as well as bug fixes / clean-ups.

With the upcoming Linux 5.20 cycle the RISC-V CPU architecture's default kernel configuration "defconfig" is being tweaked so it's capable of running Docker out-of-the-box.

RISC-V International has relayed word to us that in China the DeepComputing and Xcalibyte organizations have announced pre-orders on the first RISC-V laptop intended for developers. The "ROMA" development platform features a quad-core RISC-V processor, up to 16GB of RAM, up to 256GB of storage, and should work with most RISC-V Linux distributions.

RISC-V International announced their first batch of new specifications for 2022. This includes approving of Efficient Trace for RISC-V (E-Trace), RISC-V Supervisor Binary Interface (SBI), RISC-V UEFI, and RISC-V Zmmul multiply-only extensions.

At the Embedded World conference happening this week in Nürnberg, Think Silicon is showing off the first production RISC-V 3D GPU design.

A few days ago the RISC-V pull request landed in Linux 5.19 with support for RISC-V 32-bit (RV32) binaries on RV64, enabling the new Svpbmt extension, and other improvements. On Friday a secondary set of RISC-V changes were sent in for Linux 5.19 that includes adding the DeviceTree files for another new RISC-V board.

On Tuesday the RISC-V architecture changes were merged into the in-development Linux 5.19 kernel with several new features in tow.

With Linux 5.18 expected to be released as stable tomorrow and that opening up the Linux 5.19 merge window, feature work aimed for this next kernel should be largely wrapped up. Within the RISC-V architecture's "for-next" branch is several interesting additions.

MIPS Tech is no longer working on their MIPS CPU instruction set architecture but has been taking on RISC-V based designs. Today the company made the bold announcement for their new eVocore P8700 and I8500 multiprocessor IP cores that they offer "Best-In-Class Performance and Scalability."

Last week the main RISC-V pull for Linux 5.18 brought Sv57 five level page table support, improved PolarFire SoC support, an optimized MEMMOVE code, support for Restartable Sequences, and more. A second batch of RISC-V feature updates were sent out this week and now merged for making Linux 5.18 even better for this open processor ISA.

The RISC-V CPU architecture updates have landed for the in-development Linux 5.18 kernel.

It was just with Linux 5.17 that its RISC-V code adds "sv48" support for being able to handle more system memory by offering 48-bit virtual address space support. Now for Linux 5.17 there is "sv57" support prepared for 57-bit virtual address space support with five level page table handling.

Intel Foundry Services already courted SiFive as a customer and there were even those talks last year of Intel reportedly trying to acquire that leading RISC-V chip designer while today Intel has announced it joined RISC-V International as its latest move around this open-source processor ISA.

In addition to Linux 5.17 bringing support for the low-cost StarFive RISC-V platform among other RISC-V updates, more changes for this royalty-free processor ISA were sent in on Friday.

SiFive's HiFive Unmatched is the best, readily available RISC-V developer board at the moment with enough horsepower for modest development/porting work and continues seeing improvements with the mainline Linux kernel. But availability on HiFive Unmatched is beginning to dry up and SiFive isn't planning on any further production runs as it begins focusing on the board's successor.

The RISC-V architecture updates for the in-development Linux 5.17 kernel have been successfully submitted.

With Imagination Technologies having sold off what was MIPS Technologies several years ago and that CPU architecture having been abandoned now, Imagination today announced "Catapult" as their new family of RISC-V processor IP.

Back in October SiFive teased a new performance-optimized RISC-V core and today they finally shared more public details on this Performance P650 core.

While there was the Libre RISC-V GPU effort aiming to provide an open-source GPU accelerator based on RISC-V, it ultimately turned into Libre-SOC with a focus now on the POWER ISA. Meanwhile Vortex is continuing to mature as an open-source, FPGA-based RISC-V GPGPU processor.

The RISC-V architecture updates were sent out on Friday for targeting the nearly-over Linux 5.16 merge window.

Following the recent RISC-V Bitmanip work in Binutils, the GCC 12 compiler has now landed preliminary support for the RISC-V ISA's bit manipulation extension.

SiFive just shared word that at today's Linley Conference they teased their Performance P550 successor that will "set a new standard for the highest efficiency RISC-V processor available."

The GNU toolchain (initially with the GNU Assembler) has begun landing support for RISC-V's Zbs instructions that are part of the Bitmanip extension to the processor ISA.

Coming with the Linux 5.16 kernel cycle will be support for RISC-V virtualization with the Kernel-based Virtual Machine (KVM).

The RISC-V architecture updates have landed in the Linux 5.15 kernel with more software features now being supported.

The RISC-V architecture code supports more functionality with the in-development Linux 5.14 kernel.

SiFive today is announcing the Performance P550 as the fastest RISC-V processor yet while also announcing the Performance P270 too.

The Linux kernel's RISC-V support continues picking up remaining features not yet wired up beyond the base architecture support. The latest is transparent hugepages (THP) to be supported for RISC-V with Linux 5.14.