RISC-V News Archives

Going back to April 2024, SiFive announced the HiFive Premier P550 as an interesting RISC-V developer board to succeed their HiFive Unleashed that was a nice little RISC-V board. There were delays in shipping the HiFive Premier P550 but they have been making progress and are now ready to ship Ubuntu 24.04 LTS pre-installed on this RISC-V board. They have also lowered the pricing on these RISC-V boards.

The Linux 6.8 kernel merged the Imagination PowerVR driver as a new open-source driver for supporting the PowerVR "Rogue" graphics architecture and being developed in tandem by Imagination Tech with their upstream Mesa Vulkan driver. Initially this PowerVR driver was catering to ARM SoCs with the Rogue graphics while now the open-source driver is being extended to work on RISC-V too.

Patches from a Bytedance engineer for the Linux kernel allow for overcoming the current 4K page size limitation of RISC-V and introduce a new 64K page size option.

The RISC-V CPU port updates have been sent out for the in-development Linux 6.13 kernel.

MIPS has begun working on the open-source compiler toolchain support for their P8700 RISC-V based processors. Initial patches posted today bring-up the MIPS P8700 RISC-V support for the LLVM compiler stack.

It looks like the upcoming Linux 6.13 cycle will be adding RISC-V support for user-space pointer masking and tagged address ABI.

Earlier this year SiFive announced the HiFive Premier P550 RISC-V development board with plans for shipping in July. That timeframe for shipping since passed but SiFive today issued a new update on their RISC-V development board.

The RISC-V architecture updates have been submitted for the Linux 6.12 kernel cycle. More RISC-V CPU ISA extensions are being supported along with enabling some additional kernel features for this CPU architecture.

Back in June it was teased that Framework Computer in collaboration with DeepComputing would be releasing a RISC-V motherboard for the Framework Laptop 13. That RISC-V laptop motherboard has yet to be officially released but Linux kernel patches were posted today for enabling the DeviceTree support so Linux can boot on this upcoming board.

While RISC-V processors don't need to worry about Meltdown and Spectre or have any other severe CPU vulnerabilities at the moment, with the upcoming Linux 6.12 kernel the RISC-V code is set to enable the generic CPU vulnerabilities support.

SiFive today lifted the lid on the P870-D, its new RISC-V processor dor data center and AI workloads. The P870-D is designed to scale up to 256 cores while supporting modern features like CXL and other AI/HPC minded features.

Security researchers with the CISPA Helmholtz Center for Information Security have disclosed GhostWrite, a new CPU vulnerability affecting a common RISC-V processor.

The mainline RISC-V Linux kernel port continues to become more featureful each kernel cycle... Last week for the start of the Linux 6.11 merge window there were new RISC-V ISA extensions wired up while in ending out the v6.11 merge window this weekend there is yet more enablement activity.

Palmer Dabbelt on Saturday sent out the RISC-V architecture updates for the ongoing Linux 6.11 merge window.

The RISC-V kernel port with Linux 6.11 is introducing the ability to handle memory hot plugging/unplugging.

Ubuntu maker Canonical put out a news release today around the DC-ROMA RISC-V Laptop II that is an octa-core RISC-V laptop shipping soon with Ubuntu Linux.

Linux kernel patches were posted today for enabling Linux to boot on the LicheeRV Nano, a mini single board computer that comes in at a mere 22.86 x 35.56 mm. As interesting as the size with this SBC is the Sophgo SG2002 SoC that features a mix of RISC-V and ARM cores.

A few days ago with the main RISC-V architecture pull for Linux 6.10 was enabling Rust support within the kernel for this ISA as well as other additions. A secondary set of RISC-V changes have been merged as well ahead of the Linux 6.10 merge window closing this weekend.

The latest RISC-V port updates have been merged for the in-development Linux 6.10 kernel.

Since SiFive ceased production of the HiFive Unleashed developer board we've been clamoring for a new and more powerful RISC-V developer board... Today SiFive announced the HiFive Premier P550 as a new developer system offering that will be available this summer.

With the upcoming Linux 6.10 kernel cycle, the RISC-V architecture code is seeing kernel-mode FPU. This kernel floating point support is needed for the AMDGPU kernel graphics driver and particular its DCN display code. In turn this should allow recent AMD Radeon graphics cards to work on RISC-V with display support using the company's open-source driver stack.

The RISC-V architecture updates were sent out today for the in-development Linux 6.9 kernel ahead of the v6.9-rc1 release this Sunday.

With Linus Torvalds back to work, merged to mainline on Wednesday were the RISC-V architecture updates for the in-development Linux 6.8 kernel cycle.

In addition to the many x86/x86_64 and AArch64 improvements this round for Linux 6.7, on the RISC-V architecture side are some exciting kernel advancements too.

Patches posted this week by SiFive for the Linux kernel provide cryptographic implementations of various functions inside the Linux kernel using the processor ISA's vector crypto extensions.

As we approach the end of 2023, sadly, the real-time kernel "PREEMPT_RT" support still hasn't been mainlined... The main blocker pending is still the ongoing work around non-blocking consoles / threaded console handling to then allow the few dozen remaining out-of-tree RT kernel patches to be merged. The good news is that when the PREEMPT_RT support is ready for mainline, it looks like the RISC-V architecture support will also be real-time friendly too.

Patches have been posted to the Linux kernel mailing list in an effort to mainline support for the Milk-V Duo RISC-V development platform with the basic board retailing for $9.

More RISC-V architecture updates were merged this weekend for the ongoing Linux 6.6 merge window.

Palmer Dabbelt sent out the initial batch of RISC-V processor architecture updates for the Linux 6.6 kernel port.

The GNU Compiler Collection 14 (GCC 14) will feature support for the new RISC-V processor ISA vector cryptographic extensions.

While the upstream Linux kernel support for RISC-V continues to improve with new ISA features, support for more RISC-V SoCs, and other enhancements, in some areas the open-source RISC-V code continues to play catch-up with the other mature architectures supported by the Linux kernel. One of the areas still pending is enabling KASLR support for RISC-V on Linux to enhance system security.

Support for RISC-V's Vector ISA is now expected to be merged for the upcoming Linux 6.5 kernel merge window.

Linux Foundation Europe has announced the RISC-V Software Ecosystem (RISE) Project to help facilitate more performant, commercial-ready software for the RISC-V processor architecture.

One of the missing RISC-V features now in place for the in-development Linux 6.4 kernel is system hibernation / suspend-to-disk support.

Being merged today into the GCC 13 compiler is the set of T-Head vendor extensions to the RISC-V ISA. This set of vendor extensions is designed to augment the RISC-V ISA and provide faster and more energy efficient capabilities.

The RISC-V architecture updates were merged this Saturday for the Linux 6.3 merge window.

A Phoronix reader pointed out that there are initial code that landed for adding RISC-V processor support to Microsoft's .NET runtime.

While there has been much work on the Linux kernel's RISC-V CPU architecture support, a feature not tackled until now has been the Kernel Address Space Layout Randomization (KASLR) support for randomizing the kernel mapping to enhance system security.

While there is a lot to love about RISC-V, with the plethora of RISC-V extensions some of the acronyms are hard to digest. The latest example is the Linux kernel patches for "zisslpcfi", which is the RISC-V extension around Control-Flow Integrity (CFI) support for RISC-V processors.

While the open RISC-V processor architecture has proven to be highly successful, one of the features that it hasn't yet supported with the Linux kernel to this point has been system hibernation / suspend-to-resume, but that support is now on the way.

The RISC-V processor architecture changes were merged this week for the Linux 6.2 cycle.

If the royalty free open-source processor ISA RISC-V is to enjoy success on the Linux desktop, obviously it needs an office suite... LibreOffice as the open-source office suite alternative to Microsoft Office is now seeing proper RISC-V 64-bit support.

For those working on RISC-V software development on bare metal hardware, the in-development LLVM Clang 16 compiler has added support for allowing "-mtune=native" and "-mcpu=native" to work properly on this CPU ISA.

Not that you are likely to connect a CD/DVD drive to a RISC-V system in 2022+, but RISC-V's default kernel configuration with the upcoming Linux 6.1 kernel is adding support for CD-ROM file-systems.

Last week was the main set of RISC-V updates for Linux 6.0 that included improving Svpbmt support, a more robust default kernel configuration, and other improvements. A secondary set of RISC-V CPU architecture updates has now been merged for Linux 6.0.

Each new kernel cycle there continues to be more maturity to the RISC-V processor architecture code. With Linux 6.0 there are a few new features wired up as well as bug fixes / clean-ups.

With the upcoming Linux 5.20 cycle the RISC-V CPU architecture's default kernel configuration "defconfig" is being tweaked so it's capable of running Docker out-of-the-box.

RISC-V International has relayed word to us that in China the DeepComputing and Xcalibyte organizations have announced pre-orders on the first RISC-V laptop intended for developers. The "ROMA" development platform features a quad-core RISC-V processor, up to 16GB of RAM, up to 256GB of storage, and should work with most RISC-V Linux distributions.

RISC-V International announced their first batch of new specifications for 2022. This includes approving of Efficient Trace for RISC-V (E-Trace), RISC-V Supervisor Binary Interface (SBI), RISC-V UEFI, and RISC-V Zmmul multiply-only extensions.

At the Embedded World conference happening this week in Nürnberg, Think Silicon is showing off the first production RISC-V 3D GPU design.