Intel Details Gen11 Graphics & Sunny Cove For Icelake

Written by Michael Larabel in Intel on 12 December 2018 at 09:00 AM EST. 10 Comments
At Intel's architecture day, the company finally detailed their "Gen 11" graphics that we've been seeing open-source Linux graphics driver patches for many months (Intel OTC posted their initial open-source display driver code in early January and has continued the enablement work since) albeit elusive in substantive user details and hardware until Icelake. But today at least we can share more about the significant improvements with Gen11 graphics.

Below are the highlights, albeit a bit short given the limited turnaround time and complicated travel timing.

- Gen11 will be the company's first TeraFLOP integrated graphics processor.

- Gen11 will have a 3MB L3 cache size.

- There is tile-based rendering support to complement the immediate mode rendering.

- Memory subsystem improvements.

- Coarse pixel shading as a form of variable shading rate control. This should yield around a 1.3x real-world performance improvement in games making use of variable shading rate control. Yes, they will be looking into supporting the relevant Vulkan shader rate control functionality.

- Efficiency improvements and more for better compute performance.

- On the media side there is new HEVC video coding, HDR tone mapping, parallel decoders, and more.

- Gen11 will indeed support Adaptive-Sync! Finally! There will also be HDR display support and better support for high resolution displays.

- HEVC was the focus, but when asking about VP9/AV1 during the demo showcase... Gen11 media block will have "full" support for VP9. There is not any AV1 acceleration yet but it's "coming soon" past Gen11 and Intel is "fully committed" to AV1.

Succeeding Gen11 will be the exciting Xe graphics architecture and that's where their promising dedicated graphics ambitions come into play beginning in 2020. Xe will be their architecture for both integrated and discrete graphics. Unfortunately, not many details were shared on Xe at this EOY2018 event.

In addition to detailing Gen11 graphics, a large part of Intel's Architecture Day on Tuesday covering the Sunny Cove cores for Icelake. Due to the short time with the embargo expiry the next morning, here are those highlights.

- 5-level paging to be supported, which we've already covered the Linux kernel patches on.

- Multi-Key Total Memory Encryption and User Mode Instruction Prevention will be supported... Again, already kernel patches have been posted for them but at least now we know when it's coming to the hardware.

- Big Number Arithmetic (IFMA), Vector AES, Vector Carryless Multiply, Galois Field, and SHA extensions are coming with Icelake. Fortunately, we've seen much of the new instruction set work already land within the mainline compilers and other relevant code-bases.

- Going from four to five wide allocations, eight to ten execution ports, twice the L1 store bandwidth, and greater capabilities per execution port.

We should be seeing Icelake processors before the end of the 2019 calendar year.
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