VESA Announces eDP 1.4b, Marks Embedded DisplayPort 1.4 Production-Ready
Written by Michael Larabel in Standards on 27 October 2015 at 12:16 PM EDT. Add A Comment
VESA has just announced the latest version of their Embedded DisplayPort specification, eDP 1.4b, which marks Embedded DisplayPort 1.4 as now being under a "production-ready" status with this standard being in development for over two years.

eDP 1.4b hardware is expected to begin appearing in mid-2016. Meanwhile, CPUs and GPUs that currently support DisplayPort 1.3 are said to be compatible with the eDP 1.4 interface.

In terms of what's new with the latest VESA specification:
Like the previous eDP 1.4a standard, eDP 1.4b specifies four high-speed HBR3 lanes between the graphics adapter and display, with each lane operating at an 8.1 Gbps link rate. The lanes can be divided up between two or four independent panel segments, or used all together for a total theoretical payload bandwidth of 25.92 Gbps. One update to the original eDP 1.4 standard, which lowers system BOM cost, is an addition made to the Selective Update protocol for Panel Self Refresh. When sending the sub-frame video block for the partial update region, the Selective Update command from the video source now includes the Y-axis coordinate (line number) of where the region begins, instead of just the X-axis coordinate. Because this requires less precision in the asynchronous time base of the sink device, there is no need to include a discrete quartz crystal or crystal oscillator, as required by the original eDP 1.4 standard.

Another update to the standard is reduced granularity of the X- and Y-axis of the selective update region. Lowering the granularity can reduce the complexity of the display's remote frame buffer implementation, thereby simplifying internal video compression implementation without diminishing the advantages of eDP 1.4.

Refinements were also made to the Selective Update protocol, as well as to the Multi-SST Operation (MSO) feature and the use of Display Stream Compression (DSC), Advanced Link Power Management (ALPM), and the auxiliary channel-based frame synchronization. Some of these refinements were made to simplify system design while others were made to further clarify implementation. Other parts of the standard were also updated to improve clarity and reduce ambiguity, minimizing the hurdles to launching the eDP 1.4 ecosystem.
More details via the press release at
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