GCC 12 Merges Initial Support For RISC-V's Bitmanip Extensions
Written by Michael Larabel in RISC-V on 25 October 2021 at 05:30 AM EDT. 9 Comments
RISC-V --
Following the recent RISC-V Bitmanip work in Binutils, the GCC 12 compiler has now landed preliminary support for the RISC-V ISA's bit manipulation extension.

RISC-V's Bitmanip is a collection of several component extensions intended to help cater the open-source processor ISA for better efficiency that can result in code size reduction, better performance, and reduced energy consumption.

Merged this morning to GCC 12 Git was the initial Bitmanip extension support followed by implementing the instruction patterns and cost models for ZBA, ZBB, and ZBS extensions.

The tentative RISC-V Bitmanip extension specification can be read on GitHub.

GCC 12 with this RISC-V Bitmanip ZBA/ZBB/ZBS support should be out as stable in the form of GCC 12.1 around the end of Q1'22.
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