Intel RAO-INT Added To GCC 13, Grand Ridge & Granite Rapids CPU Targets Ready

Written by Michael Larabel in Intel on 7 November 2022 at 05:23 AM EST. Add A Comment
INTEL --
Intel compiler engineers continue being very busy working to land as much of the new CPU feature support as they can into GCC 13 for what is the next annual compiler release that will debut as GCC 13.1 in the early months of 2023.

GCC 13 in the coming days will move to its next stage of development focused on bug/regression fixing and feature work officially ending. Intel engineers recently have been working on ensuring their 2023 and 2024 processors are finding support in GCC 13 so that compiler will be stable and adopted prior to these processors reaching customers. It's great to see Intel continuing this trend of early enabling new compiler targets and supporting new instruction set extensions for processors not being released for more than a year away. Meanwhile on the other side of the table, GCC 13 is also adding Znver4 support for already-shipping AMD Zen 4 processors (as of now, still using the Zen 3 cost tables) and not to mention no early Znver5 support, with AMD continuing to be a very different story from their compiler enablement work compared to Intel.

In recent weeks new Intel x86_64 instruction set extensions have been introduced, Meteor Lake support was merged, and Sierra Forest was merged.


Intel has some notable new x86_64 instruction set extensions coming with their future CPUs.


Being posted this weekend on the mailing list and already merged is Intel RAO-INT support. The RAO-INT instructions are premiering with Grand Ridge processors for new atomic ADD / AND / OR / XOR instructions.

Following that, being merged to the GCC 13 codebase after previously being on the mailing list is the Grand Ridge CPU support and Granite Rapids CPU support so both "-march=grandridge" and "-march=graniterapids" are in place for GCC 13.
graniterapids
Intel graniterapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2, VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16, AVX512BF16, AMX-FP16 and PREFETCHI instruction set support.

grandridge
Intel Grand Ridge CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD and RAOINT instruction set support.

It's great seeing all of the Intel additions getting squared away for GCC 13 well in advance of these processors launching. The LLVM/Clang support will likely be getting buttoned up soon too, but at least there is the benefit of the six month release cycles.
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