AMD Zen 5 Compiler Support Posted For GCC - Confirms New AVX Features & More

Making for a very exciting Saturday morning, AMD just posted their initial enablement patch for plumbing Zen 5 processor support "znver5" into the GNU Compiler Collection! With GCC 14 due to be released as stable in March~April as usual for the annual compiler release, it's been frustrating to see no Zen 5 support even while Intel has already been working on Clear Water Forest and Panther Lake support with already having upstreamed Sierra Forest, Granite Rapids, and other new CPU targets months ago... Well, Granite Rapids was added to GCC in late 2022. But squeezing in as what should now be merged in time is the initial AMD Zen 5 support!

Intel has tended to upstream their new compiler support well in advance of product launches to account for GCC seeing just an annual major release and LLVM/Clang on a six-month release cycle. Plus with how Linux distributions plan around the annual GCC March~April release, for example, it's not until the Ubuntu XX.10 release where they move to a new GCC compiler version by default -- like the upcoming Ubuntu 24.04 LTS already set on GCC 13. This has meant more timely Intel compiler support for customers while AMD has tended not to post their GCC and LLVM/Clang patches until after products are announced. At times they've also relied on SUSE compiler engineers for working out that post-announcement support.

With AMD Zen 5 products not yet announced I've been concerned that GCC 14 may go without any Znver5 enablement, but this Saturday morning certainly got me excited to see a patch just arrive for carrying out that initial -march=znver5 plumbing. Most notably it notes the Zen 5 ISA capabilities:

znver5
AMD Family 1ah core based CPUs with x86-64 instruction set support. (This supersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID, WBNOINVD, PKU, VPCLMULQDQ, VAES, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD, AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, AVX512VNNI, AVX512BITALG, AVX512VPOPCNTDQ, GFNI, AVXVNNI, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, PREFETCHI and 64-bit instruction set extensions.)

Over Zen 4, this confirms AMD Zen 5 as adding AVXVNNI, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, and PREFETCHI.

It's great seeing AVX-512 VP2INTERSECT, which has been found on the Intel side since Tigerlake. MOVDIRI and MOVDIR64B have also been found on the Intel side since Tigerlake. PREFETCHI is exciting and only coming on the Intel side with Granite Rapids. Lastly is AVX-VNNI new to Zen 5 for being equivalent to AVX512-VNNI with VEX encoding. The patch reaffirms Zen 5 (Family 1Ah) CPUs having all the same ISA capabilities just as we enjoy with Zen 4 and Zen 4C... No ISA differences, thankfully, nor between server and desktops/mobile.

Also worth noting from the Znver5 compiler patch is one additional AGU pipe (4 in total) over current generation and now six ALU pipes up from four ALU pipes with Zen 4.

The initial AMD Zen 5 enablement for GCC is now on the mailing list but will hopefully be merged to GCC 14 Git shortly. It is worth noting that the Znver5 code for now is reusing the existing Znver4 scheduling model with the AMD engineer reporting that the updated model for Zen 5 will be added later.

As of writing the LLVM/Clang compiler patches for Znver5 have yet to be posted but presumably will be soon given the GCC Zen 5 patch now public and at least on the LLVM side they are dealing with just the six-month release cycle and Linux distributions tending to pull in new LLVM releases more quickly.

It's great seeing AMD get this Zen 5 compiler support for GCC out ahead of launch! Though hopefully the lead time will be even greater for future generations, such as with GCC 13 in stable Linux distributions right now already being ready with the Granite Rapids CPU target out-of-the-box. Along with the Granite Rapids GCC support in late 2022 was also Sierra Forest and Meteor Lake as well. In other compiler CPU enablement news, last night Ampere Computing posted Ampere-1B for LLVM as what is said to be their third-generation core with significant updates over Ampere-1.

Update: For added context I didn't spell out as clearly in the original article, the znver4 enablement for GCC 13 didn't land until October 2022 while the Ryzen 7000 series launched at the end of September 2022. Hence enjoying the fact of this Znver5 support coming early prior to AMD Zen 5 processors launching and being able to make it for the GCC 14.1 stable release coming up in a few weeks.