Intel Posts GCC Compiler Patches For Clear Water Forest & Panther Lake

Intel continues to do a splendid job at ensuring the open-source GCC and LLVM/Clang upstream compilers have support for their new processor cores well in advance of products shipping. Beyond already having Sierra Forest, Granite Rapids, Lunar Lake and Arrow Lake support already in upstream GCC, today one of the Intel compiler engineers sent out patches for enabling the Clear Water Forest and Panther Lake cores.

Clear Water Forest is the successor to Sierra Forest and won't be out until 2025 as their next-gen E-core Xeon processor. Panther Lake meanwhile is what will follow Lunar Lake. Panther Lake is also currently expected for release in 2025 and will use the Intel 18A process. With Meteor Lake processors not formally shipping yet, it's great to see Intel compiler support already with Meteor Lake, Arrow Lake, Lunar Lake, and now this pending Panther Lake support that should be merged in time for GCC 14.

GCC 14 stable will be out in the early months of 2024 and great to see initial Intel platform support for what will be through their 2025 hardware. Meanwhile no signs of any "znver5" target yet in GCC or LLVM/Clang with AMD on the opposite side of the table normally not posting any new open-source compiler patches until they actually have their next-generation processors shipping. Given the yearly stable release cadence to GCC and the time it takes Linux distributions to pick-up new compiler versions by default, I certainly side with Intel's approach of getting out all their new compiler bits very early on.

The Clear Water Forest patch is using the presence of the USER_MSR feature for distinguishing between it and Arrow Lake S or prior. The patch posted today notes the following ISA features of Clear Water Forest:

Intel Clear Water Forest CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4, USER_MSR and PREFETCHI instruction set support.

Notably no mention of the AVX10 level or its presence in today's patches.

Over with the Panther Lake enablement patch, its ISA features listed with today's GCC patch include:

+Intel Panther Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and PREFETCHI instruction set support.

The initial support patches for Clearwater Forest and Panther Lake are currently on the GCC mailing list under "Add Intel new cpu archs" while they should work their way into GCC Git likely in the coming days and thus still well in time for the GCC 14.1 stable release in early 2024. We'll see over the coming weeks/months what additional tuning may be on the way and if any follow-up patches present additional new instructions for these CPU cores.