LLVM Adds Support For New "Ampere1B" Third-Gen Cores From Ampere Computing
Surprising me this evening when checking on the latest LLVM Git activity was merging support for Ampere1B. There is the Ampere-1A (ampere1a) variant with Memory Tagging Extension support and other minor additions over the "ampere1" base target while now coming as a surprise is Ampere-1B.
The LLVM commit adding Ampere-1B characterizes it as their third-generation core design:
"The Ampere1B is Ampere's third-generation core implementing a superscalar, out-of-order microarchitecture with nested virtualization, speculative side-channel mitigation and architectural support for defense against ROP/JOP style software attacks.
Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all features of the second-generation Ampere1A, such as the Memory Tagging Extension and SM3/SM4 cryptography instructions."
Until a few minutes ago, I hadn't heard of Ampere1B nor seen it mentioned elsewhere.
That patch was followed by another commit to LLVM that adds a new scheduling/pipeline model:
"The Ampere1B core is enabled with a new scheduling/pipeline model, as it provides significant updates over the Ampere1 core; it reduces latencies on many instructions, has some micro-ops reassigned between the XY and X units, and provides modelling for the instructions added since Ampere1 and Ampere1A."
Sounds quite interesting but given that we are still waiting on seeing AmpereOne "Ampere1" processor availability, it will be interesting to see when Ampere1B rolls out. At least -- like Intel -- Ampere Computing has been good at getting their new core support upstreamed into LLVM Clang (and GCC) early and well ahead of product launches.
For now that's all that has apparently been made public about Ampere1B cores with Friday night LLVM Git activity.
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