AXI 1-Wire Driver Is AMD's Latest Upstreaming Effort To The Linux Kernel
Since AMD's acquisition of Xilinx and working to broaden the portfolio of offerings for the data center, more AMD-Xilinx drivers have been working their way toward the mainline Linux kernel. There's been upstreaming efforts such as the Versal EDAC driver, generating DeviceTree nodes for PCI devices, Versal watchdog driver, QDMA driver, CDX bus support, and more. The latest driver working its way toward the mainline kernel from AMD is the AXI 1-wire driver.
The AXI 1-Wire Driver was posted on the Linux kernel mailing list earlier this month and already a second revision to that driver was posted at the end of last week. This is the host driver for supporting the AMD-Xilinx 1-Wire programmable logic IP block. As explained in the patches, this 1-wire IP block is used for guaranteeing protocol timing for driving off-board devices such as thermal sensors, PROMs, and more. This AMD driver is seeking to be included as part of the Linux kernel's 1-wire "W1" subsystem.
The AMD AXI 1-wire driver is currently undergoing review on the LKML.
This AXI 1-wire IP block doesn't appear to be new IP but rather only now being submitted for mainline inclusion. There are various AMD/Xilinx AXI 1-wire references going back some months/years on Wiki documentation pages, forums, etc. In any event, it's nice seeing all of the upstreaming efforts this year on the Xilinx side.
The AXI 1-Wire Driver was posted on the Linux kernel mailing list earlier this month and already a second revision to that driver was posted at the end of last week. This is the host driver for supporting the AMD-Xilinx 1-Wire programmable logic IP block. As explained in the patches, this 1-wire IP block is used for guaranteeing protocol timing for driving off-board devices such as thermal sensors, PROMs, and more. This AMD driver is seeking to be included as part of the Linux kernel's 1-wire "W1" subsystem.
The AMD AXI 1-wire driver is currently undergoing review on the LKML.
This AXI 1-wire IP block doesn't appear to be new IP but rather only now being submitted for mainline inclusion. There are various AMD/Xilinx AXI 1-wire references going back some months/years on Wiki documentation pages, forums, etc. In any event, it's nice seeing all of the upstreaming efforts this year on the Xilinx side.
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