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AMD Zen 2 "znver2" Support Lands In LLVM Clang 9.0
Back in October is when AMD published the Znver2 compiler patch for GCC that builds atop the existing Zen "znver1" support while adding in the new instructions of Cache Line Write Back (CLWB), Read Processor ID (RDPID), and Write Back and Do Not Invalidate Cache (WBNOINVD). It was the first-cut support and still leveraged the same cost tables and scheduler data from the current-generation Zen processors. That support was quickly merged, making it for the upcoming GCC 9.1 stable compiler release, so that when these next-generation processors hit it will be possible to use -march=znver2 for generating optimized code for these 7nm AMD CPUs.
Over in the LLVM/Clang space, as of Tuesday the necessary bits landed in LLVM and Clang. Like the GCC 9 state, the same scheduler model as Znver1 is currently used and enables the CLWB / RDPID / WBNOINVD over what's found with Znver1.
As LLVM Clang 9.0 won't be shipping until September or so, there still is plenty of time for getting this Zen 2 CPU support better tuned. AMD Zen 2 CPUs are expected to begin rolling out around the middle of this year.