AMD Preparing 5-Level Paging Linux Support For Future CPUs
5-level paging is for increasing the virtual and physical address space on x86_64 systems. With 5-level paging the virtual address space goes from a 256 TiB maximum to 128 PiB while the physical address space threshold goes from 64 TiB to 4 PiB. This 5-level paging support is important for today's increasing powerful and memory intensive servers. The downside to 5-level paging is page table walks taking longer due to that extra level, but in practice that cost should be small especially with software optimizations made since Intel originally began working on 5LP support years ago.
Intel worked on the 5-level paging Linux kernel support going back five years now while on the hardware side it's just with their latest Intel Xeon Scalable 3rd Gen "Ice Lake" processors where they support 5-level paging. That support has been around since the days of Linux 4.14 while in Linux 5.5 5-level paging support is enabled by default on supported CPUs and all ironed out on more recent kernels.
While Intel's Xeon Ice Lake processors support 5-level paging, there hasn't been much (any?) public communication from AMD around their 5-level paging plans for their EPYC server processors. But out now is a new patch series in preparing the AMD SVM KVM code for 5-level page tables. Kernel changes to this AMD SVM specific code within the Kernel-based Virtual Machine is needed for handling 5-level page tables.
One of the patches does note, "AMD future CPUs will require a 5-level NPT if host CR4.LA57 is set." Setting the CR4 register bit LA57 is the same as Intel for enabling 5-level paging with supported processors. Thus the AMD 5-level paging for future (EPYC) processors is likely to be quite similar to Intel and leverage all of Intel's existing Linux kernel support. This is also confirmed by the AMD 5-level paging Linux kernel patches all being specific to just the AMD SVM code -- in this case there are some KVM changes needed to the AMD code for proper 5-level page table handling for guest VMs.
Given the timing of these patches and AMD's current practices of not usually sending out hardware enablement related CPU patches too far in advance for the Linux kernel or related open-source components (unlike Intel's established open-source track record over the past two decades), it's likely a safe bet to assume next-gen EPYC "Genoa" processors next year will be supporting 5-level paging.