Linux Kernel Developers Begin Figuring Out Vendor-Specific RISC-V Code

With the increasingly popular RISC-V open-source processor instruction set architecture (ISA), there is the possibility for vendor-specific instruction set extensions. At this point the kernel has no infrastructure in place for its RISC-V port to allow for such bits, but that is being worked on as part of bringing up AndeStar RISC-V CPUs under the Linux kernel.

RISC-V is free and open but of course the base ISA doesn't suit everyone's needs and vendors are allowed to build in their own extensions to suit their purpose. These vendor-specific extensions may or may not be compatible across a sub-set of RISC-V hardware, so the kernel needs infrastructure for being able to select RISC-V features to enable or not. It will be interesting as more RISC-V hardware comes to market and how many vendor-specific extensions will end up being employed and hopefully not fragmenting the landscape too much.

AndeStar developers are working on adding this vendor-specific infrastructure to the kernel. Their motivation for getting it in place is that their low-end RISC-V CPUs do not support a cache coherent agent. So in order for Linux to run on their hardware, they need to overcome this limitation with their own workaround.

They have proposed an implementation for handling vendor-specific RISC-V code within the kernel that is now undergoing review for possible inclusion into a future kernel release.

Separately, there's been three rounds of RISC-V architecture patches submitted for the Linux 4.20 kernel. There's ongoing work but nothing too particularly exciting about the patches for this merge window.