MIPS P8700 RISC-V CPU Support Posted For LLVM Compiler

MIPS has begun working on the open-source compiler toolchain support for their P8700 RISC-V based processors. Initial patches posted today bring-up the MIPS P8700 RISC-V support for the LLVM compiler stack.

The MIPS P8700 is one of the company's high performance RISC-V designs in their post MIPS CPU architecture era. The P8700 series supports 1 or 2 way SMT, out-of-order pipeline, a RISC-V compliant ISA, and designed to address the compute needs for automotive applications and other similar purposes.

While a RISC-V compliant processor design in rv64imafdc mode, besides enabling the Zba and Zbb extensions this LLVM CPU target is needed as the P8700 introduces two new instructions of its own around conditional moves "mipscmov" and a load/store pair instruction "mipslsp".

This morning this pull request was opened for plumbing the MIPS P8700 CPU support within LLVM. That 2.3k lines of code code is now under review for enabling the P8700 RISC-V target. MIPS is also working on the P8700 support for the GCC compiler and GNU toolchain at large along with the Linux kernel and other open-source components.