GCC 13 Adds RISC-V T-Head Vendor Extension Collection
![RISC-V](/assets/categories/risc-v.webp)
Merged to GCC 13 Git includes initial support for the XTheadBa, XTheadBb, XTheadBs, XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadInt, XTheadMac, XTheadMemIdx, XTheadMemPair, and XTheadSync extensions. These vendor extensions come from T-Head Semiconductor, which is part of Alibaba as their chip making business unit.
The T-Head RISC-V extensions are designed to provide for faster and more energy efficient RISC-V with these extensions adding new instructions around cache management, multi-processor synchronization, bit manipulation, single-bit instructions, GPR memory operations, multiply-accumulate instructions, vector dot, and more.
The GCC 13 support was merged today across a number of patches for bringing up these vendor extensions. These extensions are documented on GitHub for those curious about these T-Head additions.
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