GCC 11's x86-64 Microarchitecture Feature Levels Are Ready To Roll
These x86_64 micro-architecture feature levels have been about coming up with a few "classes" of Intel/AMD CPU processor support rather than continuing to rely on just the x86_64 baseline or targeting a specific CPU family for optimizations. These new levels make it easier to raise the base requirements around Linux x86-64 whether it be for a Linux distribution or a particular software application where the developer/ISV may be wanting to compile with greater instruction set extensions enabled in catering to more recent Intel/AMD CPUs. Having this set of four versions/levels also reduces the number of possible combinations if wanting to enable Function Multi-Versioning (FMV) or the like without resorting to every possible Intel/AMD CPU family. And we'll see what else comes of this and the effort around some distributions looking to raise the Linux x86_64 CPU requirements.
LLVM Clang 12 merged their support in October for being able to pass x86-64-v2/x86-64-v3/x86-64-v4 to -march= for specifying the feature level. GCC 11 also in October merged their support albeit forgot to write about it on my TODO list. They have their code merged and ready to go with GCC 11 due out in March~April. More recently GCC also allows configuring its compiler build using these feature levels for the "--with-arch_64=" option.
These common levels in their initial form amount to:
x86-64: CMOV, CMPXCHG8B, FPU, FXSR, MMX, FXSR, SCE, SSE, SSE2
x86-64-v2: (close to Nehalem) CMPXCHG16B, LAHF-SAHF, POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3
x86-64-v3: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE
x86-64-v4: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL
They are the same for both LLVM and GCC in being specified via the x86-64 psABI thanks to the work by Red Hat in getting this all squared away.
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