LLVM Clang 12 Merges Support For x86_64 Microarchitecture Levels

In an effort to better cater towards newer and common x86_64 instruction set extensions, open-source toolchain developers are moving ahead with the work on x86_64 micro-architecture feature levels for being able to target a handful of different "levels" beyond the base x86_64 instruction set.

The x86_64 feature levels are for easily segregating different classes of x86_64 Intel/AMD CPUs in hopes of making it easier for Linux distributions to increase their base requirements beyond just x86_64/AMD64 and improving compiler toolchains with a common set of possible levels / hardware capabilities in generating optimized libraries. This goes along with work pursued by Red Hat in raising the x86_64 CPU requirements for new RHEL/Fedora releases and for optimization initiatives like the glibc HWCAPS in supporting a few different optimization levels rather than having to target every possible Intel/AMD CPU microarchitecture family as is currently done for code optimization/tuning.

This past week LLVM Clang 12 added support for feeding the x86_64 feature levels into the Clang C/C++ compiler.

The defined x86_64 feature levels include:

x86-64: CMOV, CMPXCHG8B, FPU, FXSR, MMX, FXSR, SCE, SSE, SSE2
x86-64-v2: (close to Nehalem) CMPXCHG16B, LAHF-SAHF, POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3
x86-64-v3: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE
x86-64-v4: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL

The different levels/versions can be fed now into -march= for Clang 12 and GCC 11 if wanting to optimize for one of those targets rather than specifying specific instruction set extensions manually or a CPU family.

These baselines are laid out via the