Intel Sends In A Bunch Of New CXL Code For Linux 6.2

Written by Michael Larabel in Hardware on 11 December 2022 at 06:00 AM EST. 2 Comments
As expected, the Linux 6.2 kernel is introducing a lot more Compute Express Link (CXL) enablement code.

Intel engineers continue to lead with the CXL subsystem enablement work for the Linux kernel. With Linux 6.2 they have focused on more CXL 2.0+ enablement while also adding some additional CXL 1.x functionality.

Ahead of the Linux 6.2 merge window opening up tomorrow, the CXL pull request for the v6.2 cycle was already submitted this weekend. Dan Williams of Intel who is currently managing the CXL subsystem for the Linux kernel summed up this cycle's change as:
While it may seem backwards, the CXL update this time around includes some focus on CXL 1.x enabling where the work to date had been with CXL 2.0 (VH topologies) in mind. First generation CXL can mostly be supported via BIOS, similar to DDR, however it became clear there are use cases for OS native CXL error handling and some CXL 3.0 endpoint features can be deployed on CXL 1.x hosts (Restricted CXL Host (RCH) topologies). So, this update brings RCH topologies into the Linux CXL device model.

In support of the ongoing CXL 2.0+ enabling 2 new core kernel facilities are added. One is the ability for the kernel to flag collisions between userspace access to PCI configuration registers and kernel accesses. This is brought on by the PCIe Data-Object-Exchange (DOE) facility, a hardware mailbox over config-cycles. The other is a cpu_cache_invalidate_memregion() API that maps to wbinvd_on_all_cpus() on x86. To prevent abuse it is disabled in guest VMs and architectures that do not support it yet. The CXL paths that need it, dynamic memory region creation and security commands (erase / unlock), are disabled when it is not present.

As for the CXL 2.0+ this cycle the subsystem gains support Persistent Memory Security commands, error handling in response to PCIe AER notifications, and support for the "XOR" host bridge interleave algorithm.

That last feature, "XOR" interleave support, is built on top of the ACPICA update for this cycle.

So for Linux 6.2 there is support for Restricted CXL Host topologies, handling CXL errors via PCIe AER, support for CXL Persistent Memory Security commands, the new API for cache flushing, support for the XOR algorithm for CXL host bridge interleave, simplifying of CXL to NVDIMM interactions, and other changes.
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