x86-64-v5? Questions Arise Over The Future Of x86-64 Micro-Architecture Feature Levels

While recently there has been more Linux distribution vendor interest in evaluating x86-64-v2 and/or x86-64-v3 baselines for future Linux distribution releases as well as offering optimized packages for higher x86-64 baselines either for x86-64-v3 with being able to assume AVX/AVX2 or in the x86-64-v4 level where AVX-512 is introduced, the prospect of x86-64 micro-architecture feature levels for future processors isn't clear.

The x86-64 micro-architecture levels were established in the first place by engineers from Red Hat, SUSE, Intel, and AMD that were picked up by the GCC/GNU toolchain and then LLVM for coming up with sane feature levels beyond the x86_64 baseline specifications. These have worked out well with x86-64-v2 encompassing useful additions and rather robustly supported by any non-obsolete x86_64 CPUs, x86-64-v3 adding AVX/AVX2 and other ISA features of the past decade, and then x86-64-v4 for AVX-512. But what about x86-64-v5 or any future iterations?

The possibility of x86-64-v5 was raised this week on the LLVM Discourse. Lawrence Benson with TU Munich was raising the possibility of a x86-64-v5 target that could encompass CPU ISA features of the very latest AMD and Intel CPUs. The hypothetical x86-64-v5 could fit well for AMD Zen 4 and Intel Icelake Server and newer. It also makes sense having a stepping stone prior to AVX10 rolling out.

That would make sense though no visible action on x86-64-v5 has happened yet. Phoebe Wang of Intel raised the matter that they have been having issue as well internally with how to handle x86-64 micro-architecture feature levels with respect to AVX10. With AVX10 making a maximum vector length of either 256 or 512-bit, AVX 512-bit isn't necessarily guaranteed and thus hard to incorporate into an x86-64 feature level if a lot of CPU cores end up only going for 256-bit support... Or it could end up being a moot point if the future Intel/AMD CPUs tend to go the 512-bit route in practice. But otherwise newer CPUs may be restricted to lower feature levels depending upon how the versions are structured.

"Yes, how to perfectly arrange AVX10 256-bit to x86-64-vN is a headache problem. We have some internal discussions and haven’t made any consensus. Suggestions are welcome!"

So it will be interesting to see how future AVX10 iterations play out and if new x86-64 feature level versions reach consensus.