OpenRISC + RISC-V Improvements Come For Linux 5.11

Written by Michael Larabel in Hardware on 18 December 2020 at 09:41 AM EST. 2 Comments
The OpenRISC and RISC-V processor architecture updates have both been submitted for the ongoing Linux 5.11 merge window.

OpenRISC, the open-source RISC-based ISA now in the works for two decades but still without any dedicated open-source ASIC in the wild, is seeing new platform support with Linux 5.11. The OpenRISC pull brings a LiteX SoC controller driver and other support around LiteX for OpenRISC. LiteX is a Migen/MiSoC CPU/SoC builder for deployments on FPGAs. LiteX already supports soft-core implementations of PicoRV32, VexRISCV, and others.

This LiteX OpenRISC support with the mainline Linux 5.11 kernel is around a mor1kx soft CPU for white LiteX already has upstream support as well for that target. Besides the OpenRISC support for the LiteX platform, the few other changes amount to fixes.

The RISC-V changes for Linux 5.11 include support for the contiguous memory allocator (CMA), IRQ time accounting, stack tracing, strict /dev/mem, kernel section protection, and more.
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