GCC Lands Support For The MIPS16e2 ISA

Written by Michael Larabel in GNU on 3 July 2023 at 06:09 AM EDT. 2 Comments
The in-development GCC 14 compiler has added support for the MIPS16e2 processor ISA.

MIPS16e2 is an extension of the MIPS16e instruction set and compatible with the MIPS32 and MIPS64 instruction sets. The MIPS16e2 ASE adds eight general purpose registers and several special purpose registers and defines new instructions for helping to increase code density. There are new instructions with MIPS16e2 around caching, load/store word left/right, LUI, bitwise, MOVx instructions, and more. Those interested can find all the MIPS16e2 details via the specification.

A set of patches by Jie Mei were merged overnight to GCC Git for enabling MIPS16e2 support. The MIPS16e2 specification originates from 2014 while only now did any open-source developers get around to implementing it.

The newly merged MIPS16e2 support is accessible via the -mmips16e2 switch.
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