GCC 12 Compiler Squaring Away Its AVX-512 FP16 Support
This summer Intel posted public documentation around AVX-512 FP16 that allows for full-speed handling of FP16 values compared to the existing AVX-512 support for larger data types. Intel is adding AVX-512 FP16 to future Xeon processors (seemingly with Sapphire Rapids) to help with machine learning workloads and other cases where half-precision floating point numbers are sufficient and this will allow for greater performance.
Back in August on the LLVM/Clang compiler front Intel began landing their AVX512-FP16 support in LLVM/Clang 14 for release early next year. Those LLVM patches were merged and in more recent weeks the attention has turned to the GCC compiler.
Over the past few weeks and the most recent activity as of last week, the GCC AVX512-FP16 patches have landed and appears now to have the bulk of the code in place.
This AVX512-FP16 landing comes ahead of GCC 12 transitioning to stage three development next month. GCC 12.1 as the first GCC 12 stable release as usual should come out around the start of Q2, right around the time Intel is expected to be ramping Sapphire Rapids. Usually by now Intel would have most of their new instruction set extensions and other tuning well already mainlined and found in stable versions of GCC (and Clang) though this time around there still has been new code flowing in given all of the changes abound with Sapphire Rapids and especially big additions like AMX.
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