IBM Lands Last Minute POWER10 Updates Into GCC 11 Compiler

Written by Michael Larabel in GNU on 22 March 2021 at 01:12 PM EDT. 5 Comments
In addition to the last minute AMD Zen 3 "znver3" tuning in GCC 11, also landing rather late are scheduling updates for the GNU Compiler Collection around the IBM POWER10 processor target.

Initial POWER10 support for the GCC compiler has been brewing for two years now. Even prior to IBM formally announcing POWER10, the enablement work started out in 2019 as the "future" POWER processor target and POWERXX. Since then that work on ensuring good POWER10 ISA support has continued and with GCC 11 should be in good shape.

The latest work is POWER10 scheduling updates and additional instruction costs that were merged on Friday night. That should help ensure the GCC compiler makes more optimal decisions when targeting POWER10.

Up to now the scheduling description for POWER10 was a copy of POWER9 but has now been better adapted for the changes in the ISA. Code comments do confirm that POWER10 can now dispatch up to 8 iops per cycle rather than 6 iops per cycle with POWER9. POWER10 has a maximum of 4 VSU / 2 Load / 2 Store per cycle. Details on the POWER10 changes in full can be found via this commit.

It's great continuing to see IBM be very punctual with their POWER10 compiler support that has been building up for two years. These 7nm POWER processors should begin shipping in H2'2021 -- at least that was the plan as of last November while it's not clear if there have been any delays as a result of the ongoing chip shortages, etc. It will be interesting to see how these POWER10 processors can compete with EPYC 7003 Milan and Ice Lake Xeon processors.
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