IBM Begins Plumbing "Future" Processor Into GCC Compiler - POWER10?
IBM engineers have landed initial support for "-mcpu=future" into the GCC compiler... As they say in the commit message, "a future architecture level, as yet unnamed."
This IBM "future" processor is being added to the POWER architecture code succeeding POWER9. More than likely, its the early enablement work for POWER10.
There have been talk of IBM/OpenPOWER POWER10 processors coming on a 10nm process in 2020 and it looks like they are getting that compiler toolchain support into GCC 10. POWER10 is expected to better compete with Intel 2nd Gen Xeon Scalable and AMD EPYC "Rome" processors and offer better performance-per-watt and deep learning / big data capabilities over POWER9. POWER10 will continue to feature PCI Express 4.0 as well as the latest NVIDIA NVLink and other updated capabilities. Public details on POWER10 are still light.
As of today in GCC SVN/Git, it simply adds the new future target without exposing any new architectural details. Expect more POWER "future" processor enablement to happen in this open-source compiler toolchain soon.
This IBM "future" processor is being added to the POWER architecture code succeeding POWER9. More than likely, its the early enablement work for POWER10.
There have been talk of IBM/OpenPOWER POWER10 processors coming on a 10nm process in 2020 and it looks like they are getting that compiler toolchain support into GCC 10. POWER10 is expected to better compete with Intel 2nd Gen Xeon Scalable and AMD EPYC "Rome" processors and offer better performance-per-watt and deep learning / big data capabilities over POWER9. POWER10 will continue to feature PCI Express 4.0 as well as the latest NVIDIA NVLink and other updated capabilities. Public details on POWER10 are still light.
As of today in GCC SVN/Git, it simply adds the new future target without exposing any new architectural details. Expect more POWER "future" processor enablement to happen in this open-source compiler toolchain soon.
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