GCC 10 Lands Support For Emulating MMX With SSE Instructions

The GCC 10 code compiler merged support to begin emulating MMX intrinsics using SSE.

Back in February we wrote about the patches by Intel for implementing MMX intrinsics using SSE instructions. For those still relying upon MMX SIMD instructions, the benefit of implementing it using SSE is that it frees up an 8-byte vectorizer for SSE2 when MMX is disabled. Presumably, future Intel CPUs might end up retiring MMX at long last.

Now that GCC 9 has been released and GCC 10 in the early stages of development, prolific Intel toolchain developer H.J. Lu merged all of the MMX emulation code into the compiler for next year's GCC 10.1 release.

MMX has been around since 1997 with the P5 Pentium processors while has long been superseded by SSE and AVX for modern SIMD.