GCC 10 Lands Support For Intel Tiger Lake's AVX-512 VP2INTERSECT
Similar to the recent LLVM compiler work, the in-development GCC 10 compiler also now has support for the AVX-512 VP2INTERSECT instructions being introduced on Intel Tiger Lake CPUs.
VP2INTERSECT was disclosed in May's architecture programming reference manual from Intel. This new AVX-512 addition is for computing an intersection between DWORDS/QUADWORDS to a pair of mask registers. Tiger Lake where this support will debut is Intel's Icelake successor with Willow Cove core.
There's more still due to Tiger Lake compiler support/optimizations, but now at least VP2INTERSECTD and VP2INTERSECTQ is there to match the LLVM commits from a few weeks ago.
VP2INTERSECT was disclosed in May's architecture programming reference manual from Intel. This new AVX-512 addition is for computing an intersection between DWORDS/QUADWORDS to a pair of mask registers. Tiger Lake where this support will debut is Intel's Icelake successor with Willow Cove core.
There's more still due to Tiger Lake compiler support/optimizations, but now at least VP2INTERSECTD and VP2INTERSECTQ is there to match the LLVM commits from a few weeks ago.
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