Compiler Support Getting Wired Up For AVX-512 VP2INTERSECT

Written by Michael Larabel in LLVM on 31 May 2019 at 06:45 AM EDT. 1 Comment
AVX-512 is being further extended with future Intel CPUs. LLVM Clang is now the first open-source compiler seeing support for Tiger Lake's VP2INTERSECT instructions.

Yesterday I wrote about initial compiler support landing for Intel's Sapphire Rapids Icelake successor with the new Enqueue Stores "ENQCMD" seeing support in both LLVM and GCC. Waking up this morning, attention turned to AVX-512 VP2INTERSECT and that support has made it first into LLVM/Clang while no GCC support at the time of writing but it can't be far behind.

AVX-512 VP2INTERSECT was first disclosed by this month's update to the Intel architecture programming reference manual. The manual confirms AVX512_VP2INTERSECT is coming with their "Tiger Lake" microarchitecture. Tiger Lake is the Icelake successor aiming for release in 2020 and targeting workstations/desktops/mobile with a Willow Cove core. Details are still light on this 10nm+ CPU but at least it's now known the AVX-512 is being further enhanced there.

VP2INTERSECT is for computing an intersection between DWORDS/QUADWORDS to a pair of mask registers.

As of today Intel's compiler engineers have merged AVX-512 VP2INTERSECT support into LLVM and the Clang front-end bits. As there is no "-march=tigerlake" target yet for LLVM/Clang, this VP2INTERSECT support is just being exposed via the "-mavx512vp2intersect" compiler flag.

This initial AVX-512 VP2INTERSECT support for Tiger Lake will be part of the ~September release of LLVM 9.0.
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