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AMD Readies Linux Patches For x2AVIC Support
With AMD's Advanced Virtual Interrupt Controller (AVIC) code for the past number of years, x2APIC has not been supported concurrently. Now with x2AVIC it overcomes that limitation for interrupt virtualization with x2APIC enabled. X2APIC is particularly important for supporting larger vCPU counts ahead of AMD's next-generation server processors with EPYC Genoa expected to have 96 cores / 192 threads per socket and EPYC Bergamo up to 128 cores / 256 threads per socket... Or even further out, AMD EPYC Turin rumored to have 256 cores / 512 threads per socket. The x2AVIC code has been successfully tested now by AMD engineers with more than 255 vCPUs active, verifying its functionality up to 512 vCPUs for now with their internal hardware.
Current generation EPYC 7003 "Milan" processors offer up to 64 cores / 128 threads per socket.
Previously, with AVIC, guest needs to disable x2APIC capability and can only run in APIC mode to activate hardware-accelerated interrupt virtualization. With x2AVIC, guest can run in x2APIC mode. This feature is indicated by the CPUID Fn8000_000A EDX, and it can be activated by setting bit 31 (enable AVIC) and bit 30 (x2APIC mode) of VMCB offset 60h.
The mode of interrupt virtualization can dynamically change during runtime. For example, when AVIC is enabled, the hypervisor currently keeps track of the AVIC activation and set the VMCB bit 31 accordingly. With x2AVIC, the guest OS can also switch between APIC and x2APIC modes during runtime. The kvm_amd driver needs to also keep track and set the VMCB bit 30 accordingly.
More details on AMD's x2APIC virtualization support for Linux KVM usage via this patch series.