AMD Hardware-Accelerated Virtualized IOMMU Patches Posted For Linux
The AMD Hardware Accelerated Virtualized IOMMU functionality provides partial hardware-acceleration for implementing guest IOMMUs with virtualizing the guest command buffer, guest event log, and guest PPR log. Ultimately the work is about improving PCI pass-through I/O performance while still providing guest I/O protection.
The patch series sent out on Wednesday by AMD Linux engineer Suravee Suthikulpanit further adds:
"In addition, this feature can be used in combination with nested IOMMU page tables to accelerated address translation from GIOVA to GPA. In this case, the host page table (a.k.a stage2 or v1) is managed by the hypervisor (i.e. KVM/VFIO) and the guest page table (a.k.a stage1 or v2) is managed by the guest IOMMU driver (e.g. when booting guest kernel with amd_iommu=pgtable_v2 mode).
Since the IOMMU hardware virtualizes the guest command buffer, this allows IOMMU operations to be accelerated such as invalidation of guest pages (i.e. stage1) when the command is issued by the guest kernel without intervention from the hypervisor.
This series is implemented on top of the IOMMUFD framework. It leverages the exisiting APIs and ioctls for providing guest iommu information (i.e. struct iommu_hw_info_amd), and allowing guest to provide guest page table information (i.e. struct iommu_hwpt_amd_v2) for setting up user domain."
The AMD IOMMU work in this direction has been happening for a while so it's good to see it moving closer.
Back in 2021 AMD presented at the kVM Forum conference around their prototype effort at that point. Wednesday's patches are still marked as a "request for comments" as they finalize on the implementation and hopefully reach the mainline Linux kernel in the not too distant future.
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