AMD Picasso APUs To Support VCN Dynamic Power Gating
Written by Michael Larabel in AMD on 25 September 2018 at 05:26 PM EDT. 1 Comment
AMD --
Earlier this month AMD sent out the initial Linux graphics driver patches for "Picasso" APUs and now a new patch series today sheds some light on a new capability for these new APUs reported to be similar to current Raven Ridge hardware.

While the initial AMDGPU DRM driver Picasso code drop happened earlier this month -- and it's already been queued for Linux 4.20~5.0 along with initial Raven 2 support -- as is usually the case, over weeks/months that follow are more of the new feature work for the driver gets ironed out beyond the initial hardware enablement.

The first set of patches post-enablement for Picasso hardware were quietly sent out today with not much exposure... Just ending the patch series with a "Enable DPG mode on PCO." That PCO is short for Picasso while "DPG" in this context is for Dynamic Power Gating.

Dynamic power gating is about shutting off power to unused hardware blocks depending upon the current system activity. Previous generations of AMD APUs have supported dynamic power gating while for the Picasso APUs it's being extended through to the VCN block -- Video Core Next. VCN premiered with Raven Ridge for video encode/decode/transcode as a unified block over UVD and VCE on previous hardware.

In digging through the eight patches the DPG support for Picasso with VCN is sorted out. But the patch comments don't reveal any notable details -- it will certainly be interesting to see once Picasso hardware surfaces but should end up delivering better power-savings. Improving the power efficiency is likely one of the broader goals with Picasso given these yet-to-be-released APUs are also expected to be manufactured at 12nm compared to the current 14nm FinFET Raven Ridge processors.
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