SiFive Tapes Out Their First 5nm RISC-V Processor Core

Written by Michael Larabel in RISC-V on 13 April 2021 at 09:25 AM EDT. 36 Comments
SiFive's OpenFive business unit announced today they have completed their first tape out of a RISC-V processor core using TSMC's 5nm process.

This 5nm RISC-V SoC will be for "advanced AI/HPC" solutions using a chiplet architecture with SiFive 7-Series processor IP and OpenFive HBM3 IP subsystem.

SiFive announced their 5nm RISC-V processor tape out on their blog.

Via their press release outlines more details, including the use of SiFive E76 32-bit CPU. They expect the first 5nm silicon to be available in Q2'2021.
The SoC features an OpenFive High Bandwidth Memory (HBM3) IP subsystem and D2D I/Os, as well as a SiFive E76 32-bit CPU core. The HBM3 interface supports 7.2Gbps speeds allowing high throughput memories to feed domain-specific accelerators in compute-intensive applications including HPC, AI, Networking, and Storage. OpenFive’s low-power, low-latency, and highly scalable D2D interface technology allows for expanding compute performance by connecting multiple dice together using an organic substrate or a silicon interposer in a 2.5D package.

The SiFive E76 is a 32-bit RISC-V core designed for delivering high perfomance in power-constrained environments. More details on the SiFive E76 via its IP product page.
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