x86 CPU Changes For Linux 5.3 Bring Intel UMWAIT, Zhaoxin, Engineering Train Wreck

Written by Michael Larabel in Linux Kernel on 8 July 2019 at 09:30 AM EDT. 2 Comments
Thomas Gleixner sent in his various x86 code updates early this morning for the just kicked off Linux 5.3 kernel cycle.

Some of the notable x86 CPU changes for Linux 5.3 include:

- Official x86 Zhaoxin CPU support for these Chinese desktop CPU processors based on VIA Centaur IP. There were some kernel patches last year for Zhaoxin while with this next kernel release the support appears in order.

- Intel UMWAIT support for a Tremont core feature to help with power-savings during idle periods.

- Speeding up MTRR handling code for CPUs that can handle cache self-snooping. This can speed-up the MTRR setup by "a factor of 50."

- FSGSBASE support was added for better performance at long last. FSGSBASE has been around on the Intel side since the Ivy Bridge days... But just days ago the FSGSBASE code was then dropped over fundamental problems with the code. So it's being added now but then immediately reverted, so it will not be in Linux 5.3. Gleixner refers to this latest work as "Yet another engineering trainwreck..."

More details on the x86 CPU changes for Linux 5.3 via this pull request. Also are x86/pti updates that this cycle plug a few more theoretical Spectre / MDS leaks.
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