Libre-SOC Still Persevering To Be A Hybrid CPU/GPU That's 100% Open-Source
The project that started off as Libre-RISC-V with aims to be a Vulkan accelerator but then decided on the OpenPOWER ISA rather than RISC-V is still moving ahead under the "Libre-SOC" branding.
Libre-SOC continues to be led by Luke Kenneth Casson Leighton and this week he presented both at the OpenPOWER Summit and X.Org Developers' Conference (XDC2020) on his Libre-SOC dreams of having a 100% fully open SoC on both the software and hardware sides while being a hybrid CPU/GPU. Similar to the original plans when targeting RISC-V that it would effectively be a SoC but with new vector instructions optimized for graphics workloads, that's still the plan albeit now using OpenPOWER as a base.
Libre-SOC is still going at it thanks in large part to NLnet grants and with OpenPOWER rather than RISC-V due to having been turned off by secret/private mailing lists and other transparency issues.
Libre-SOC is still in the early design stages and is working first on an FPGA implementation while also working on figuring out ISA extensions needed for making OpenPOWER more suitable to graphics workloads.
The project's end-game remains to be a mass-volume, low-power embedded SoC that will work out for netbooks, tablets, smartphones, IoT, and other small form factors. This SoC would have no DRM restrictions and fully open-source. Whether they can hit their objectives remains to be seen though with their previously-stated target being 25 FPS @ 720p, 5~6 GFLOPS.
The two Libre-SoC presentations this week are largely similar and can be found via this slide deck.
Libre-SOC continues to be led by Luke Kenneth Casson Leighton and this week he presented both at the OpenPOWER Summit and X.Org Developers' Conference (XDC2020) on his Libre-SOC dreams of having a 100% fully open SoC on both the software and hardware sides while being a hybrid CPU/GPU. Similar to the original plans when targeting RISC-V that it would effectively be a SoC but with new vector instructions optimized for graphics workloads, that's still the plan albeit now using OpenPOWER as a base.
Libre-SOC is still going at it thanks in large part to NLnet grants and with OpenPOWER rather than RISC-V due to having been turned off by secret/private mailing lists and other transparency issues.
Libre-SOC is still in the early design stages and is working first on an FPGA implementation while also working on figuring out ISA extensions needed for making OpenPOWER more suitable to graphics workloads.
The project's end-game remains to be a mass-volume, low-power embedded SoC that will work out for netbooks, tablets, smartphones, IoT, and other small form factors. This SoC would have no DRM restrictions and fully open-source. Whether they can hit their objectives remains to be seen though with their previously-stated target being 25 FPS @ 720p, 5~6 GFLOPS.
The two Libre-SoC presentations this week are largely similar and can be found via this slide deck.
174 Comments