LLVM Begins Preparing For Intel Sierra Forest & Grand Ridge CPUs

Written by Michael Larabel in Intel on 19 October 2022 at 06:12 AM EDT. 2 Comments
INTEL --
Last week saw Intel sending out new GCC compiler patches for adding the "Sierra Forest" CPU target and the number of new x86_64 instructions it's adding. Those GCC patches follow Intel publishing an updated programming reference manual where they detailed these new instructions coming for Sierra Forest Xeon CPUs as well as Grand Ridge. Now on the LLVM compiler side, they too have begun landing new patches for these new Intel instructions.

The first of the Sierra Forest / Grand Ridge enablement work landing overnight in LLVM 16 is adding WRMSRNS instructions and MSRLIST instructions -- both new to Sierra Forest and Grand Ridge.

The MSRLIST instructions are RDMSRLIST for reading a list of model specific registers and WRMSRLIST for writing a list of model specific registers. These new RDMSRLIST/WRMSRLIST instructions allow supplying a list of up to 64 model specific registers at a time by this instruction compared to RDMSR/WRMSR instructions that are an MSR at a time.

Also added so far to LLVM is WRMSRNS. The WRMSRNS with Grand Ridge and Sierra Forest is a non-serializing write to a model specific register. Rather than WRMSR being a serialized instruction, WRMSRNS is a non-serializing write but otherwise behaves the same.


Last month's Intel programming reference manual update also noted several more instructions coming with Sierra Forest and Ridge Ridge, including CMPCCXADD, AVX-IFMA, AVX-NE-CONVERT, and AVX-VNNI-INT8. So far those additional instructions haven't landed in LLVM Git nor the "-march=sierraforest" target but given Intel's usual punctuality around the compiler patches they will probably come soon. These parts likely won't be out until 2024 meanwhile LLVM Git has yet to see any AMD Zen 4 (znver4) target and tuned support added for these already shipping processors.
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