Intel Begins Preparing Linux Graphics Driver For Multi-Tile Hardware

Written by Michael Larabel in Intel on 9 October 2021 at 10:25 AM EDT. 14 Comments
Intel has been preparing Xe HP bring-up for many months already including fundamental work around their discrete graphics/accelerator support for their Linux graphics driver stack going back quite a while. On the Xe HP front, Friday afternoon brought an important patch series posted for the first time: initial work around multi-tile support.

Intel Xe HP / Ponte Vecchio introduces the notion of a multi-tile / chiplet design. So far the Intel Linux graphics driver has only been built around a single tile design but the patches sent out on Friday afternoon begin the infrastructure changes in the i915 kernel DRM driver to support multiple tiles.

The patch cover lever summed up the current state of affairs:
Some of our upcoming platforms, including the Xe_HP SDV, support a "multi-tile" design. A multi-tile platform is effectively a platform with multiple GT instances and local memory regions, all behind a single PCI device. From an i915 perspective, this translates to multiple intel_gt structures per drm_i915_private. This series provides the initial refactoring to support multiple independent GTs per card, but further work (especially related to local memory) will be required to fully enable a multi-tile platform.

Note that the presence of multiple GTs is largely transparent to userspace. A multi-tile platform will advertise a larger list of engines to userspace, but the concept of "tile" is not something userspace has to worry about directly. There will be some uapi implications later due to the devices having multiple local memory regions, but that aspect of multi-tile is not covered by this patch series and will show up in future work.

That initial basket of multi-tile code is now out for review. Though given that more work around the local memory handling is needed, it's unlikely to see this buttoned up in time for the next 5.16 cycle.
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