Intel Begins Drafting AVX10 Plans For The LLVM/Clang Compiler
Announced in July was AVX10 as Intel's successor to AVX512 and will excitingly come to future Core hybrid CPUs across both P and E cores. With AVX10 there is mandated 256-bit support while the 512-bit vector size is optional and will be found with the P core implementations. Due to a number of changes with AVX10 compared to the AVX-512 way of doing things, special care is being taken in drafting the new compiler support.
Phoebe Wang of Intel Shanghai has drafted a LLVM discussion thread for helping to design the AVX10 feature support.
"To enable this feature in LLVM, we have some unique challenges as well as design choices compared to traditional ISA enablement. It is also a peculiar ISA in which no new instructions are introduced in the initial version. It looks more like a re-organization of the AVX512 instructions in LLVM rather than introducing anything brand new here.
Considering the large among of re-organizing work, the preference of each proposal from developer and user, we are requesting for comments before we complete the final implementation. We also welcome collaboration from community to do the re-organization together."
New AVX10 options similar to what's found with the proposed GCC compiler patches are suggested. There are also other design elements still to be settled. With the proposed LLVM design choices there are some differences to the current GCC patches, but in the end hopefully it will have similar parity across GCC and Clang to avoid any user/developer confusion.
With the initial basic "AVX10.1" support not expected until Granite Rapids server processors and coming to P/E-core client processors after that, there still is a lot of time for Intel and the open-source compiler community to sort out the optimal path forward.
25 Comments
