Intel Linear Address Masking "LAM" Ready For Linux 6.2
Intel Linear Address Masking (LAM) allows software to make use of untranslated address bits of 64-bit linear addresses for metadata. Linear addresses use either 48-bits (4-level paging) or 57-bits (5-level paging) while LAM allows the remaining space of the 64-bit linear addresses to be used for metadata.
Intel outlined Linear Address Masking since 2020 in their programming reference manual but has so far only acknowledged it coming with "future" processors. So far I haven't seen Intel explicitly indicate whether the upcoming Sapphire Rapids Xeon processors will support LAM or not.
For the past several months Intel has been revising their LAM kernel patches for all the kernel-side changes to support Linear Address Masking, in addition to their compiler-side patches and other software ecosystem work.
This LPC 2021 presentation by Intel engineer H.J. Lu has more information on the LAM for Linux work.
After a lot of work, it looks like for Linux 6.2 the Intel LAM support is ready to go.
The Intel LAM kernel patches have been queued up into TIP's x86/mm branch. So barring any new issues from coming up in the next few weeks, the LAM kernel patches will be submitted for the Linux 6.2 merge window in December for finally getting the LAM kernel API ready for use by user-space applications.
AMD meanwhile with Zen 4 has their equivalent of LAM as UAI. AMD Upper Address Ignore is similarly about using the extra bits of an address as arbitrary software-assigned and software-interpreted tags. The AMD route is also going through new prctl() options for this tagged user addresses support. While present with Zen 4 processors, AMD's UAI support hasn't yet been queued for merging into the mainline Linux kernel.