GNU Binutils 2.40 Branched With Zstd Support, Zen 4, New Intel Instructions

Written by Michael Larabel in GNU on 2 January 2023 at 06:58 AM EST. 9 Comments
With the start of the new year also came the branching of GNU Binutils 2.40 ahead of its expected stable release around early February.

GNU Binutils 2.40 has now been branched as binutils-2_40-branch for separating the development now from Git master as it works towards the official v2.40 release in the weeks ahead. As usual, new GNU Binutils releases tend to come out like clockwork in early February and August for their six-month cycles.

Among the changes developers can find with GNU Binutils 2.40 include:

- The objdump utility adds a "--show-all-symbols" option for displaying all symbols that match a given address when disassembling rather than just printing only the first match.

- There is now a "--enable-colored-disassembly" option when configuring the Binutils build to optionally enable colored output support when running within the terminal. Colored output is disabled by default.

- Objcopy's --decomporess-debug-sections now supports dealing with Zstd compressed debug sections. Similarly, the --compress-debug-sections=zstd is now supported for using Zstd to compress debug sections. Additionally, addr2line and objdump --dwarf now support Zstd compressed debug sections too.

- The readelf and objdump commands now has a "--sframe" option for dumping SFrame sections.

- GNU Gold now supports Zstd-compressed debug sections.

- The linker also adds -w / --no-warnings options to suppress the generation of any warnings or error messages if there is a need to create a known, non-working binary.

- AMD Zen 4 "znver4" support.

The GNU Assembler (Gas) with Binutils 2.40 adds:

- Support for many new Intel x86_64 instructions including RAO-INT, AVX-NE-CONVERT, MSRLIST, WRMSRNS, CMPccXADD. AVX-VNNI-INT8, AVX-IFMA, PREFETCHI, and AMX-FP16.

- Similar to the other Binutils changes for supporting Zstd compression, Gas now supports Zstd compressed debug sections.

- Support for various T-Head extensions found on the Allwinner D1 RISC-V SoC.

- Support for the RISC-V Zawrs extension, which is the "Wait-on-Reservation-Set" extension for used in polling loops that allows a core to enter a low-power state and wait on a store to a memory location.

- Support for the Arm Cortex-X1C.

- The new Gas "--gsframe" option can be used for generating SFrame unwind information on x86_64 and AArch64.
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