GCC 15 Merges Support For Intel APX NF

The latest feature work around Intel's Advanced Performance Extensions (APX) that is merged for the in-development GCC 15 compiler is supporting APX NF functionality for suppressing the update of status flags on arithmetic operations.

APX NF is for suppressing the updating of status flags with various operations. The APX NF is short for "No Flags" and can be used with the instructions: INC, DEC, NEG, ADD, SUB, AND, OR, XOR, SAL, SAR, SHL, SHR, ROL, ROR, SHLD, SHRD, IMUL, IDIV, MUL, DIV, LZCNT, TZCNT and POPCNT. The EVEX.NF mode for APX is part of the ISA improvements presented by the Advanced Performance Extensions and avoiding the status flags writes can be to a performance advantage.

As of today in GCC 15 Git, APX NF is merged with supporting the "No Flags" mode for the common instructions where supported.

Intel's compiler engineers have been very busy preparing Advanced Performance Extensions support for both the GCC and LLVM/Clang compilers. Intel APX is quite exciting with also adding more general purpose registers, optimized register state save/restores, a new 64-bit absolute direct jump instruction, and other new capabilities.