Ampere Adds "Ampere1" CPU Core Support To LLVM
Ampere's current-generation Ampere Altra and Ampere Altra Max processors are already very competitive with up to 128 physical cores per socket and leverage an Arm Neoverse-N1 7nm design. However, as noted last year, Ampere has begun working on their own core designs for slated introduction later in 2022.
"Ampere Next-Generation" last year was confirmed to be 5nm based and have an Arm ISA compliant design and next-generation memory (DDR5) and storage capabilities. Details, however, remain light for this Ampere Altra / Altra Max successor that will usher in their own core designs. Ampere's 2022 design has also been referenced by the "Siryn" codename.
Thus I was excited to see this morning that being mainlined into LLVM was "Ampere1". Initial compiler support for the "ampere1" target is added and is compliant with the Armv8.6-A ISA. This at least confirms Armv8.6-A usage for this initial in-house Ampere core design rather than Armv9 but already a significant improvement over Armv8.2 with the Neoverse N1 cores.
The Ampere1 compiler target confirms Armv8.6-A with FP16 and MTE (Memory Tagging) extensions along with enabling the Speculation Barrier (SB) and (Speculative Store Bypass Safe (SSBS) options. This LLVM support patches the Ampere-1 support added to the GCC compiler back in November.
This patch adds in the basic "ampere1" support and a follow-on patch adds Ampere1 support for the "native" target option. These patches are in Git for what will debut as part of LLVM 15.0 this autumn.
We should be hearing more about the new Ampere CPU core design when the processor release approaches later this year. It's not even clear yet if "Ampere 1" will be part of the brand name of their upcoming processors or if "ampere1" is simply used as an alternative codename to "Siryn" or placeholder for the time being -- just as we see elsewhere when it comes to early compiler support for unreleased CPUs.
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