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AMD Is Ready To Land Zen Processor Support In The GCC Compiler
AMD's Venkataramanan Kumar sent out the znver1 enablement patch for Zen again this past week on the GCC mailing list. The patch adds the new "znver1" AMD Family 17h Zen processor support while for now the costs and tuning tables are copied from GCC's "bdver4" Excavator and there's still some adjustments to be done to the scheduler.
That latest patch can be found on gcc-patches and since then upstream GCC developers have responded that the patch looks okay for landing into trunk, meaning it will be in their mainline development code-base that will turn into GCC 6.1 next year.
AMD Zen CPUs are detected in the GCC patch by the presence of the CLZERO instruction, which is new to the hardware. CLZERO zeroes out the 64-byte cache line specified in the RAX. GCC's AMD Zen znver1 targeting with this patch exposes the BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, and POPCNT instruction set extensions.
AMD Zen hardware is expected to be available in 2016 and will largely make or break AMD's financial outlook going forward. Zen was designed in part by legendary CPU designer Jim Keller who once again left AMD last month. Compared to Bulldozer, Zen is focused on greater per-core performance and will utilize an SMT design.