More Open-Source Patches Continue Surfacing For AMD's Sabrina SoC
Over the past month I've been seeing numerous references to the AMD "Sabrina" SoC in open-source patch series, mostly when it comes to the open-source Coreboot code. We haven't seen Sabrina mentioned on AMD roadmaps, unless it's another Linux-specific codename being used by AMD for early platform enablement. But with Sabrina's Coreboot support being focused on, AMD's contributions there have been largely driven by Google and their requirements for Chromebooks / Chrome OS powered devices.
Reaffirming the Chromebook avenue, Coreboot has merged support for the "Skyrim" mainboard as a unreleased device making use of the AMD Sabrina SoC. Much of the Sabrina code within Coreboot is based on the existing AMD Cezanne code.
Sabrina has a CPU ID of Family 19h Model A0h. Some of the other open-source patches for Sabrina point to this SoC having a next-gen Audio Co-Processor "Gen2", Sabrina exclusively uses LPDDR5 memory, and other new additions. But at the same time it's rather odd that Sabrina does away with ACPI CPPC (Collaborative Processor Performance Controls) that is used now on Linux by the new AMD P-State driver. It's unknown why ACPI CPPC support is removed for Sabrina. So at this point we have many open questions around the AMD Sabrina SoC support but at least we continue seeing more open-source/Linux patches around it thanks to the Chromebook aim.