Xilinx ZynqMP DisplayPort DRM/KMS Driver Could Soon Be Ready For Mainline

Back in January there were Xilinx developers who posted a DRM/KMS driver for their DisplayPort subsystem as part of the ZynqMP SoC. It looks like the driver for this display pipeline may soon be ready for mainline.

Hyun Kwon of Xilinx posted the latest "XLNX" DRM driver patches on Sunday for their ZynqMP DP KMS code. This driver in its current form is just under six thousand lines of code.

The driver has now up to its eighth round of public review by upstream developers. Hyun Kwon mentions with the V8 patches he is primarily waiting on the sign-off by upstream embedded DRM driver developer Laurent Pinchart.

Xilinx has various platforms for display, where users can create using multiple IPs in the programmable FPGA fabric, or where some hardened pipeline is available on the chip. Furthermore, hardened pipeline can also interact with soft logics in FPGA.

The Xilinx DRM KMS module is to integrate multiple subdevices and to represent the entire pipeline as a single DRM device. The module includes helper (ex, framebuffer and gem helpers) and glue logic (ex, crtc interface) functions.

These latest patches for now can be found on the dri-devel list but hopefully come Linux 4.19 or 5.0 it will be ready for mainline.