Mesa 19.3 Has The Very Preliminary OpenGL + Vulkan Driver Support Ready For Intel Gen12
Similar to the flurry of Radeon driver activity in buttoning things up ahead of the Mesa 19.3 feature freeze, the Intel open-source crew has landed some last-minute bits around the Tiger Lake "Gen 12" enablement.
In recent months there has been a lot of Intel Tiger Lake / Gen12 Linux enablement activity. On the kernel side Linux 5.4 has the initial bits to be evolved over the coming cycles. Meanwhile over in user-space the initial "Iris" OpenGL and "ANV" Vulkan driver support is in place for Mesa 19.3.
Landing today included filling out more of the preliminary device information bits for Gen12/Tigerlake. These bits are sometimes just placeholders ahead of actual firm data and also refer to the maximums, but they reveal today for Gen12:
- The maximum number of vertex shader threads is at 546, compared to 364 for Gen11 or 336 for Gen9.
- The maximum number of geometry shader threads is set to 336, down from 364 for Gen11 and the same as Gen9.
- The maximum number of tessellation threads is 546, a similar increase compared to Icelake and Skylake as with the other thread counts.
- The maximum number of compute shader threads has risen from 56 on Gen9 and Gen11 to 112 threads per DSS with Gen12.
The Tiger Lake Gen12 PCI IDs initially added are GT1 parts of 0x9A60, 0x9A68, 0x9A70, and 0x9A78. The Gen12 GT2 parts are 0x9A40, 0x9A49, and 0x9A59.
Expect more Tiger Lake activity during the Mesa 20.0 cycle and future kernel/Mesa releases over the year ahead. At this point the first Tiger Lake CPUs along with the first Intel Xe discrete graphics solutions based on Gen12 aren't expected until H2'2020.
In recent months there has been a lot of Intel Tiger Lake / Gen12 Linux enablement activity. On the kernel side Linux 5.4 has the initial bits to be evolved over the coming cycles. Meanwhile over in user-space the initial "Iris" OpenGL and "ANV" Vulkan driver support is in place for Mesa 19.3.
Landing today included filling out more of the preliminary device information bits for Gen12/Tigerlake. These bits are sometimes just placeholders ahead of actual firm data and also refer to the maximums, but they reveal today for Gen12:
- The maximum number of vertex shader threads is at 546, compared to 364 for Gen11 or 336 for Gen9.
- The maximum number of geometry shader threads is set to 336, down from 364 for Gen11 and the same as Gen9.
- The maximum number of tessellation threads is 546, a similar increase compared to Icelake and Skylake as with the other thread counts.
- The maximum number of compute shader threads has risen from 56 on Gen9 and Gen11 to 112 threads per DSS with Gen12.
The Tiger Lake Gen12 PCI IDs initially added are GT1 parts of 0x9A60, 0x9A68, 0x9A70, and 0x9A78. The Gen12 GT2 parts are 0x9A40, 0x9A49, and 0x9A59.
Expect more Tiger Lake activity during the Mesa 20.0 cycle and future kernel/Mesa releases over the year ahead. At this point the first Tiger Lake CPUs along with the first Intel Xe discrete graphics solutions based on Gen12 aren't expected until H2'2020.
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