AMD Lands Displayable DCC Support For Raven APUs In Mesa 19.1's RadeonSI

Written by Michael Larabel in Mesa on 4 April 2019 at 10:22 AM EDT. 33 Comments
Marek Olšák of AMD has merged his latest performance-enhancing feature into RadeonSI Gallium3D: the enabling of displayable DCC on Raven Ridge / Raven 2 APUs.

One month back Marek originally published the patches exposing displayable DCC for Raven Ridge and now the code has been merged into Mesa Git for the Mesa 19.1 cycle. This functionality allows for scan-out surfaces to utilize delta color compression (DCC) for the potential to conserve memory bandwidth and in turn to increase performance. RadeonSI has offered DCC support but not for scan-out surfaces, which now works for Raven GFX9 hardware.

The RadeonSI bits depend upon updated patches to the AMDGPU DRM kernel driver that are queued into the Linux 5.1 kernel.

The support was merged this morning across several commits although no official word on the performance changes to expect.

My Ryzen 5 2400G box still has been hit-or-miss on Linux depending upon the latest BIOS version and Linux kernel, but will give it another go shortly to see how the performance is looking with Linux 5.1 + Mesa 19.1 for Raven Ridge.
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