ARMv9 Scalable Matrix Extension Support Lands In Linux 5.19
The 64-bit Arm (AArch64) architecture changes have been merged into the in-development Linux 5.19 kernel.
Most notable with the AArch64/ARM64 changes for Linux 5.19 is the initial kernel-side support for Arm's Scalable Matrix Extension (SME).
Arm's Scalable Matrix Extension with ARMv9-A builds on the existing Scalable Vector Extensions SVE/SVE2 to allow for matrix tile storage, load/store/insert/extract tile vectors, outer product of SVE vectors, and a streaming SVE mode. The Streaming SVE Mode with SME enables the new SME storage and instructions plus a subset of SVE2 instructions while leaving the streaming mode leads to behavior that is unchanged from SVE2.
Linux 5.19 has the initial ARMv9 SME support. At this point one notable missing piece is there is no KVM virtualization support for SME so that is disabled for VM guests. Presumably though the ARMv9 SME support for guests will come later.
The ARM64 pull also has crashkernel reservation improvements, perf updates, various code clean-ups, and various other low-level CPU arch code improvements.
Most notable with the AArch64/ARM64 changes for Linux 5.19 is the initial kernel-side support for Arm's Scalable Matrix Extension (SME).
Arm's Scalable Matrix Extension with ARMv9-A builds on the existing Scalable Vector Extensions SVE/SVE2 to allow for matrix tile storage, load/store/insert/extract tile vectors, outer product of SVE vectors, and a streaming SVE mode. The Streaming SVE Mode with SME enables the new SME storage and instructions plus a subset of SVE2 instructions while leaving the streaming mode leads to behavior that is unchanged from SVE2.
Linux 5.19 has the initial ARMv9 SME support. At this point one notable missing piece is there is no KVM virtualization support for SME so that is disabled for VM guests. Presumably though the ARMv9 SME support for guests will come later.
The ARM64 pull also has crashkernel reservation improvements, perf updates, various code clean-ups, and various other low-level CPU arch code improvements.
2 Comments