LLVM 16 Enabling Scalable Vectorization By Default For RISC-V
LLVM developer Philip Reames has flipped on scalable vectorization by default for supported RISC-V targets with Zve or V extensions. He explained with the change:
This change enables vectorization (using scalable vectorization only, fixed vectors are not yet enabled) for RISCV when vector instructions are available for the target configuration.
At this point, the resulting configuration should be both stable (e.g. no crashes), and profitable (i.e. few cases where scalar loops beat vector ones), but is not going to be particularly well tuned (i.e. we emit the best possible vector loop). The goal of this change is to align testing across organizations and ensure the default configuration matches what downstreams are using as closely as possible.
This exposes a large amount of code which hasn't otherwise been on by default, and thus may not have been fully exercised. Given that, having issues fall out is not unexpected. If you find issues, please make sure to include as much information as you can when reverting this change.
Two days have passed and so far no reverts, so it's hopefully looking good. More details for those interested via reviews.llvm.org. With this change being at the start of the LLVM 16 development cycle, there still is plenty of time to improve the compiler's RISC-V vectorization support before the stable release not until around March.
The RISC-V "V" is the complete vector math extension for this royalty-free CPU architecture while Zve is a "modest" subset of it intended for smaller cores within embedded devices and micro-controllers. RISC-V's Vector Extension 1.0 has been frozen since last year and considered stable enough to begin software work. The RISC-V V 1.0 spec for those interested can be found via GitHub.