LLVM 16 Enabling Scalable Vectorization By Default For RISC-V

[phoronix]

Phoronix: LLVM 16 Enabling Scalable Vectorization By Default For RISC-V

With LLVM 15 branched and main now open for LLVM 16, one of the early changes for this next compiler release cycle is enabling scalable vectorization by default for RISC-V with supported targets for RISC-V vector instructions...

https://www.phoronix.com/news/LLVM-RISC-V-Vectorization-Def

[kiffmet]

RISC-V is great for embedded microcontrollers/CPUs and may one day be comparable to current devices, but I don't think we'll see high-end designs aiming to compete with state of the art X86 or ARM devices any time soon. Developments in this regard have been exceptionally slow and there doesn't seem to be much ambition to do so anyways. I'm still hoping for OpenPOWER to take that spot, since it's in a much better starting position.

[coder]

I don't think we'll see high-end designs aiming to compete with state of the art X86 or ARM devices any time soon.

Well, there's a bit of an ecosystem or chicken-and-egg problem there. However, China seems very committed to RISC-V, so that probably puts a lot of momentum behind getting RISC-V into high-end mobile and cloud deployments.

Also, if/when Intel or AMD would decide to jump in with both feet, a lot could change in a hurry.