5+ Years Late: LLVM's AMD Excavator Target Was Missing Two Features

It took until 2020 for an Intel developer to land a patch providing support for two instructions supported by AMD "Excavator" CPUs but not exposed by the "bdver4" target.

It turns out LLVM's bdver4 target for Excavator CPUs was missing MOVBE and RDRND features. RDRND is for the RdRand hardware random number generator that was new to Excavator / Bulldozer v4. MOVBE is the Big Endian move instruction for going to/from x86 Little Endian format, basically reversing the byte order. MOVBE was also new to AMD CPUs starting with Excavator. RDRND is for calling on the CPU's RdRand capabilities while the MOVBE instruction can be useful in networking processing and related areas when needing to switch endianness.

In 2014 AMD sent out the GCC patch adding RDRND/MOVBE to the bdver4 compiler target but it took six years until those features were exposed by the LLVM/Clang compiler's bdver4 target.

It wasn't AMD that noticed the support missing but rather one of Intel's compiler engineers who was working on better handling how LLVM defines CPU features for Clang and auditing the correctness. In doing so, he noticed the bdver4 difference and was kind enough to land a patch so making use of "-march=bdver4" can now make use of MOVBE and RDRND if relevant for the code being compiled.

Granted, if you are making use of AMD Excavator in 2020 I would encourage you to highly consider the latest Zen 2 CPUs or the upcoming Zen 3 for much better performance and power efficiency, but unfortunate it took this long for the LLVM compiler deficiency to be noticed.